Create atmega328 abstraction

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MicroChip. ATmega328/P AVR MCU with picoPower Technology Data Sheet. 2018. (PDF)

Registers

• 11. AVR CPU Core
• 11.3.1 SREG: Status Register
• 11.4 r0..r31: General Purpose Register File
• 11.4.1 The X-register, Y-register, and Z-register
• 11.5 Stack Pointer
   
• 12. AVR Memories
• 12.6.2 EEARH, EEARL: EEPROM Address Register Low and High Byte
• 12.6.3 EEDR : EEPROM Data Register
• 12.6.4 EECR : EEPROM Control Register
• 12.6.5 GPIOR2: General Purpose I/O Register 2
• 12.6.6 GPIOR1: General Purpose I/O Register 1
• 12.6.7 GPIOR0: General Purpose I/O Register 0
   
• 13. System Clock and Clock Options
• 13.12.1 OSCCAL: Oscillator Calibration Register
• 13.12.2 CLKPR : Clock Prescaler Register
   
• 14. Power Management and Sleep Modes
• 14.12.1 SMCR : Sleep Mode Control Register
• 14.12.2 MCUCR: MCU Control Register
• 14.12.3 PRR : Power Reduction Register
   
• 15. System Control and Reset
• 15.9.1 MCUSR : MCU Status Register
• 15.9.2 WDTCSR: Watchdog Timer Control Register
   
• 16. Interrupts
• 16.2.1 Moving Interrupts Between Application and Boot Space
• 16.2.2 MCUCR: MCU Control Register
   
• 17. EXTINT - External Interrupts
• 17.2.1 EICRA : External Interrupt Control Register A
• 17.2.2 EIMSK : External Interrupt Mask Register
• 17.2.3 EIFR : External Interrupt Flag Register
• 17.2.4 PCICR : Pin Change Interrupt Control Register
• 17.2.5 PCIFR : Pin Change Interrupt Flag Register
• 17.2.6 PCMSK2: Pin Change Mask Register 2
• 17.2.7 PCMSK1: Pin Change Mask Register 1
• 17.2.8 PCMSK0: Pin Change Mask Register 0
   
• 18. I/O-Ports
• 18.4.1 MCUCR: MCU Control Register
• 18.4.2 PORTB: Port B Data Register
• 18.4.3 DDRB : Port B Data Direction Register
• 18.4.4 PINB : Port B Input Pins Address
• 18.4.5 PORTC: Port C Data Register
• 18.4.6 DDRC : Port C Data Direction Register
• 18.4.7 PINC : Port C Input Pins Address
• 18.4.8 PORTD: Port D Data Register
• 18.4.9 DDRD : Port D Data Direction Register
• 18.4.10 PIND : Port D Input Pins Address
   
• 19. 8-bit Timer/Counter0 (TC0) with PWM
• 19.9.1 TCCR0A: TC0 Control Register A
• 19.9.2 TCCR0B: TC0 Control Register B
• 19.9.3 TIMSK0: TC0 Interrupt Mask Register
• 19.9.4 GTCCR : General Timer/Counter Control Register
• 19.9.5 TCNT0 : TC0 Counter Value Register
• 19.9.6 OCR0A : TC0 Output Compare Register A
• 19.9.7 OCR0B : TC0 Output Compare Register B
• 19.9.8 TIFR0 : TC0 Interrupt Flag Register
   
• 20. 16-bit Timer/Counter1 (TC1) with PWM
• 20.15.1 TCCR0A: TC1 Control Register A
• 20.15.2 TCCR0B: TC1 Control Register B
• 20.15.3 TCCR0C: TC1 Control Register C
• 20.15.4 TCNT1L, TCNT1H: TC1 Counter Value Low and High byte
• 20.15.5 ICR1L , ICR1H: Input Capture Register 1 Low and High byte
• 20.15.6 OCR1AL, OCR1AH: Output Compare Register 1 A Low and High byte
• 20.15.7 OCR1BL, OCR1BH: Output Compare Register 1 B Low and High byte
• 20.15.8 TIMSK1: Timer/Counter 1 Interrupt Mask Register
• 20.15.9 TIFR1 : TC1 Interrupt Flag Register
   
• 21. Timer/Counter 0, 1 Prescalers
• 21.4.1 General Timer/Counter Control Register
   
• 22. 8-bit Timer/Counter2 (TC2) with PWM and Asynchronous Operation
• 22.11.1 TCCR2A: TC2 Control Register A
• 22.11.2 TCCR2B: TC2 Control Register B
• 22.11.3 TCNT2 : TC2 Counter Value Register
• 22.11.4 OCR2A : TC2 Output Compare Register A
• 22.11.5 OCR2B : TC2 Output Compare Register B
• 22.11.6 TIMSK2: TC2 Interrupt Mask Register
• 22.11.7 TIFR2 : TC2 Interrupt Flag Register
• 22.11.8 ASSR : Asynchronous Status Register
• 22.11.9 GTCCR : General Timer/Counter Control Register
   
• 23. Serial Peripheral Interface (SPI)
• 23.5.1 SPCR0: SPI Control Register 0
• 23.5.2 SPSR0: SPI Status Register 0
• 23.5.3 SPDR0: SPI Data Register 0
   
• 24. Universal Synchronous Asynchronous Receiver Transceiver (USART)
• 24.12.1 UDR0: USART I/O Data Register 0
• 24.12.2 UCSR0A: USART Control and Status Register 0 A
• 24.12.3 UCSR0B: USART Control and Status Register 0 B
• 24.12.4 UCSR0C: USART Control and Status Register 0 C
• 24.12.5 UBRR0L, UBRR0H: USART Baud Rate 0 Register Low and High byte
   
• 25. USART in SPI (USARTSPI) Mode
• See 24
   
• 26. Two-Wire Serial Interface (TWI)
• 26.9.1 TWBR : TWI Bit Rate Register
• 26.9.2 TWSR : TWI Status Register
• 26.9.3 TWAR : TWI (Slave) Address Register
• 26.9.4 TWDR : TWI Data Register
• 26.9.5 TWCR : TWI Control Register
• 26.9.6 TWAMR: TWI (Slave) Address Mask Register
   
• 27. Analog Comparator (AC)
• 27.3.1 ACSR : Analog Comparator Control and Status Register
• 27.3.2 DIDR1: Digital Input Disable Register 1
   
• 28. Analog-to-Digital Converter (ADC)
• 28.9.1 ADMUX : ADC Multiplexer Selection Register
• 28.9.2 ADCSRA: ADC Control and Status Register A
• 28.9.3 ADCL, ADCH: ADC Data Register Low and High Byte (ADLAR=0)
• 28.9.4 ADCL, ADCH: ADC Data Register Low and High Byte (ADLAR=1)
• 28.9.5 ADCSRB: ADC Control and Status Register B
• 28.9.6 DIDR0 : Digital Input Disable Register 0
   
• 29. debugWIRE On-chip Debug System
• 29.6.1 DWDR: debugWire Data Register
   
• 30. Boot Loader Support – Read-While-Write Self-programming (BTLDR)
• 30.9.1 SPMCSR: Store Program Memory Control and Status Register