stage2: sparc64: Fix & optimize 64-bit truncRegister

mapuaptu · Jun 6, 2022 · 8b70abf · 8b70abf
1 parent 4d50e52
commit 8b70abf
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/src/arch/sparc64/CodeGen.zig b/src/arch/sparc64/CodeGen.zig
@@ -3569,11 +3569,13 @@ fn truncRegister(
             });
         },
         64 => {
+            if (dest_reg == operand_reg)
+                return; // Copy register to itself; nothing to do.
             _ = try self.addInst(.{
                 .tag = .mov,
                 .data = .{
                     .arithmetic_2op = .{
-                        .is_imm = true,
+                        .is_imm = false,
                         .rs1 = dest_reg,
                         .rs2_or_imm = .{ .rs2 = operand_reg },
                     },