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cpu/we32000: Corrected several mnemonics in the WE32100 disassembler - #16112
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* Opcodes 52/53 (branch on carry clear) lost the halfword/byte displacement suffix and both disassembled as "BCC" instead of "BCCH"/"BCCB". * Opcode 60 disassembled as "RVS", which is opcode 68. It is "RVC", consistent with the BVCH/BVCB branches decoded in the same group. * SPOPRT/SPOPT2 were selected on bit 4 of the opcode, which is always clear for opcodes 00-07, so opcodes 06/07 disassembled as SPOPRD/SPOPD2 and the two mnemonics were unreachable. Bit 2 is what distinguishes 06/07 from 02/03.
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I was reading through the WE32100 disassembler and noticed that the branch case for opcode group 0x50 formats
BIT(op, 0) ? "BCC" : "BCC", so both displacement forms print the same text. Every other conditional branch in that switch appends B or H, and 0x52/0x53 are BCCH/BCCB (BGEUH/BGEUB under the other spelling of the same condition). Looking at the neighbouring cases turned up two more mistakes:BIT(op, 4), but this case only ever sees opcodes 0x00-0x07, so bit 4 is always clear there. Opcodes 0x06 and 0x07 consequently disassemble as SPOPRD and SPOPD2, and the SPOPRT/SPOPT2 spellings are unreachable. Bit 2 is what separates 0x06/0x07 from 0x02/0x03.I cross-checked the three opcode values against the WE32100 opcode table in SIMH's 3B2 simulator, which agrees: 0x52 BCCH, 0x53 BCCB, 0x60 RVC, 0x06 SPOPRT, 0x07 SPOPT2.
To check the behaviour I compiled
we32100d.cppon its own againstdisasmintf.cppandstrformat.cppwith a small driver that feeds it one opcode at a time, and dumped all 256 opcodes before and after. Before the change 0x52, 0x53, 0x60, 0x06 and 0x07 come out as BCC, BCC, RVS, SPOPRD and SPOPD2; after it they come out as BCCH, BCCB, RVC, SPOPRT and SPOPT2, and the opcodes I did not touch (0x02, 0x03, 0x5b, 0x63, 0x68) are unchanged. That standalone build is all I was able to do here, since I have no SDL development packages on this machine for a full MAME build; the change is four literals and one bit index in a single file, with no interface change.I have no WE32100 system to run, and the CPU core is still a skeleton, so this only affects debugger and unidasm output.
Per the contributing guidelines: this change was prepared with AI assistance, using Claude Opus 5 through Claude Code.