This project is an attempt for a full AES67 Hardware/Embedded implementation. A FPGA and MCU is used, currently for the dev setup a Cyclone 10LP and STM32H753ZI. The STM32 uses Zephyr. Some boilerplate code was LLM generated.
For transparency, this is primarely a learning project for me. I have never worked with FPGAs before and the only embedded experiences I've had before were not more than attaching a temperature sensor to an ESP32.
Roadmap:
FPGA:
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(DONE) Send Ethernet Frames
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(DONE) Receive Ethernet Frames
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(DONE) Send RTP Audio Packets
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Receive RTP Audio Packets
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(DONE) SPI Ethernet Interface, but a bit slow
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(DONE) FMC Ethernet Access for STM32H7
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(DONE) Add Timestamping to Ethernet MAC
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Clock Servo for Audio Clocks derived from PTPv2
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Add Control Registers to SPI
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Move MDIO to MCU
MCU
- (DONE) Custom Ethernet SPI Driver for communication to/from FPGA
- (DONE) Add Timestamping Support to SPI Driver
- Add Timestamping Support to FMC Driver
- SDP Support
- SAP Support
- mDNS Support
- Managment (Web?)interface
- FPGA Bitstream Upload