[top, csrng, entropy_src] Remove CS AES halt request interface

[vogelpi]

This interface adds considerable design and verification complexity without substantial gain: The two crypto primitives serialized by this interface (unmasked AES core inside CSRNG, unmasked SHA3 inside ENTROPY_SRC) amount to less than 40 kGE together. Much more logic than this got removed through the CSRNG restructuring effort.

At the same time, the interface is the main source of back pressure inside the ENTROPY_SRC thereby introducing the need for additional logic to aborb this back pressure. For this reason, the interface was anyway disabled for Darjeeling which uses a high-rate noise source.

This commit removes the interface completely from the top levels and the two involved hardware block IPs CSRNG and ENTROPY_SRC.

This resolves #28819.

This PR is based on top of #28804 and will be rebased once the PR is merged. Please only review the last commit.

[glaserf]

Thanks for this PR which really removes some further complexity from the entropy complex. This looks good to me, I only have some very minor comments.

I also checked out your branch to search the repo for any leftovers of the AES halt interface. I only found the following (link to master such that it won't die if you rebase your branch):

opentitan/hw/ip/csrng/data/csrng_testplan.hjson

Line 78 in a49b553

Verify that when AES_HALT is set during a generate command that no request is sent to the AES block.

[vogelpi]

Thanks for your reviews @glaserf and @phani-lowrisc , I've now addressed your comments.

[Razer6]

@vogelpi Does this have impact on the size of the distribution FIFO of Darjeeling? Giving that it's entropy source runs at a different rate?

[vogelpi]

@vogelpi Does this have impact on the size of the distribution FIFO of Darjeeling? Giving that it's entropy source runs at a different rate?

No it doesn't. Because Darjeeling did disable this interface (with a parameter) for the exact same reason. When disabling the parameter, I lowered the depth of the FIFO from 26 to 11 entries.

[vogelpi]

CHANGE AUTHORIZED: hw/ip/csrng/data/csrng.hjson
CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng.sv
CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_block_encrypt.sv
CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_core.sv
CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_ctr_drbg.sv
CHANGE AUTHORIZED: hw/ip/entropy_src/data/entropy_src.hjson
CHANGE AUTHORIZED: hw/ip/entropy_src/rtl/entropy_src.sv
CHANGE AUTHORIZED: hw/ip/entropy_src/rtl/entropy_src_core.sv
CHANGE AUTHORIZED: hw/ip/entropy_src/rtl/entropy_src_enable_delay.sv
CHANGE AUTHORIZED: hw/ip/entropy_src/rtl/entropy_src_pkg.sv
CHANGE AUTHORIZED: hw/top_earlgrey/data/top_earlgrey.hjson
CHANGE AUTHORIZED: hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

This PR reduces overall complexity by removing a feature which has no clear benefit. It has been discussed in the Silicon and Integrated WG meeting on 2025-11-25. This is fine.

[Razer6]

CHANGE AUTHORIZED: hw/ip/csrng/data/csrng.hjson
CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng.sv
CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_block_encrypt.sv
CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_core.sv
CHANGE AUTHORIZED: hw/ip/csrng/rtl/csrng_ctr_drbg.sv
CHANGE AUTHORIZED: hw/ip/entropy_src/data/entropy_src.hjson
CHANGE AUTHORIZED: hw/ip/entropy_src/rtl/entropy_src.sv
CHANGE AUTHORIZED: hw/ip/entropy_src/rtl/entropy_src_core.sv
CHANGE AUTHORIZED: hw/ip/entropy_src/rtl/entropy_src_enable_delay.sv
CHANGE AUTHORIZED: hw/ip/entropy_src/rtl/entropy_src_pkg.sv
CHANGE AUTHORIZED: hw/top_earlgrey/data/top_earlgrey.hjson
CHANGE AUTHORIZED: hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

This PR reduces overall complexity by removing a feature which has no clear benefit. It has been discussed in the Silicon and Integrated WG meeting on 2025-11-25. This is fine.