Description

Timing closure for the spi_host IP can be made easier by sampling read data from a feedback clock, instead of the internal (pre-output) clock. In other words, the data required time can be pushed out (and become less sensitive to various environmental factors) if we use the output clock's pad input to clock the first flop for read data.

This could also be implemented in spi_device for the half-cycle-sampled register in the read pipeline. However, we do already have the full-cycle variant (bypassing the half-cycle flop), and as long as there are no bizarre hold time cases where full-cycle sampling runs into troubles, it might not be necessary.

Should we do this for the M4 milestone?