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Process completed with exit code 1.

[verible-verilog-lint] reported by reviewdog 🐶 Declared module does not match the first dot-delimited component of file name: "prim_xilinx_ultrascale_pad_wrapper" [Style: file-names] [module-filename] Raw Output: message:"Declared module does not match the first dot-delimited component of file name: \"prim_xilinx_ultrascale_pad_wrapper\" [Style: file-names] [module-filename]" location:{path:"./hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_pad_wrapper.sv" range:{start:{line:10 column:8}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

[verible-verilog-lint] reported by reviewdog 🐶 Declared module does not match the first dot-delimited component of file name: "prim_xilinx_clock_buf" [Style: file-names] [module-filename] Raw Output: message:"Declared module does not match the first dot-delimited component of file name: \"prim_xilinx_clock_buf\" [Style: file-names] [module-filename]" location:{path:"./hw/ip/prim_xilinx/rtl/prim_xilinx_clock_buf.sv" range:{start:{line:5 column:8}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

[verible-verilog-lint] reported by reviewdog 🐶 Declared module does not match the first dot-delimited component of file name: "prim_xilinx_ultrascale_clock_buf" [Style: file-names] [module-filename] Raw Output: message:"Declared module does not match the first dot-delimited component of file name: \"prim_xilinx_ultrascale_clock_buf\" [Style: file-names] [module-filename]" location:{path:"./hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_buf.sv" range:{start:{line:5 column:8}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

[verible-verilog-lint] reported by reviewdog 🐶 Declared module does not match the first dot-delimited component of file name: "prim_xilinx_pad_wrapper" [Style: file-names] [module-filename] Raw Output: message:"Declared module does not match the first dot-delimited component of file name: \"prim_xilinx_pad_wrapper\" [Style: file-names] [module-filename]" location:{path:"./hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv" range:{start:{line:10 column:8}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

[verible-verilog-lint] reported by reviewdog 🐶 Declared module does not match the first dot-delimited component of file name: "prim_xilinx_xor2" [Style: file-names] [module-filename] Raw Output: message:"Declared module does not match the first dot-delimited component of file name: \"prim_xilinx_xor2\" [Style: file-names] [module-filename]" location:{path:"./hw/ip/prim_xilinx/rtl/prim_xilinx_xor2.sv" range:{start:{line:9 column:8}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

[verible-verilog-lint] reported by reviewdog 🐶 Declared module does not match the first dot-delimited component of file name: "prim_xilinx_ultrascale_xor2" [Style: file-names] [module-filename] Raw Output: message:"Declared module does not match the first dot-delimited component of file name: \"prim_xilinx_ultrascale_xor2\" [Style: file-names] [module-filename]" location:{path:"./hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_xor2.sv" range:{start:{line:9 column:8}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

[verible-verilog-lint] reported by reviewdog 🐶 Declared module does not match the first dot-delimited component of file name: "prim_xilinx_buf" [Style: file-names] [module-filename] Raw Output: message:"Declared module does not match the first dot-delimited component of file name: \"prim_xilinx_buf\" [Style: file-names] [module-filename]" location:{path:"./hw/ip/prim_xilinx/rtl/prim_xilinx_buf.sv" range:{start:{line:7 column:8}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

[verible-verilog-lint] reported by reviewdog 🐶 Declared module does not match the first dot-delimited component of file name: "prim_xilinx_ultrascale_flop" [Style: file-names] [module-filename] Raw Output: message:"Declared module does not match the first dot-delimited component of file name: \"prim_xilinx_ultrascale_flop\" [Style: file-names] [module-filename]" location:{path:"./hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_flop.sv" range:{start:{line:9 column:8}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

[verible-verilog-lint] reported by reviewdog 🐶 Declared module does not match the first dot-delimited component of file name: "prim_xilinx_ultrascale_clock_div" [Style: file-names] [module-filename] Raw Output: message:"Declared module does not match the first dot-delimited component of file name: \"prim_xilinx_ultrascale_clock_div\" [Style: file-names] [module-filename]" location:{path:"./hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_clock_div.sv" range:{start:{line:7 column:8}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}