Manual modelsim compilation and simulation errors

[chaitalisathe]

@tangxifan For the benchmark C432.v (ISCAS '85) with 36 inputs and 7 outputs, 160 total gates and 62 LUTs, total simulation time = #77496 ns, the iverilog simulation froze in between. so I am using modelsim, with modelsim I faced issue for "default nettype none" and explicit definition missing errors. For the time being I have commented out that line with those changes I am able to run the simulation with modelsim now. But I am getting all undefined outputs on FPGA out.

To reproduce the issue:
Benchmark = c432 from ISCAS' 85

configuration_chain protocol: task.cofig is read as-

Configuration file for running experiments

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

timeout_each_job : FPGA Task script splits fpga flow into multiple jobs

Each job execute fpga_flow script on combination of architecture & benchmark

timeout_each_job is timeout for each job

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 10*10
fpga_flow=yosys_vpr
#fpga_flow=yosys
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
#openfpga_vpr_device_layout=
openfpga_vpr_device_layout=--device auto
openfpga_fast_configuration=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
[BENCHMARKS]
bench23=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iscas_rtl/c432.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common =
bench23_top = c432
bench23_chan_width = 900
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=

Please let me know how to resolve this issue with 1) modesim compilation error 2) undefined FPGA outputs
I am getting following error for all components in files generated under ./SRC/ folder.
** while parsing file included at ./SRC/fabric_netlists.v(15)
** at ./SRC/sub_module/inv_buf_passgate.v(14): (vlog-2892) Net type of 'const0' was not explicitly declared.

** while parsing file included at ./SRC/fabric_netlists.v(15)
** at ./SRC/sub_module/inv_buf_passgate.v(14): (vlog-2892) Net type of 'const0' was not explicitly declared.

#1448

Thank you,
Chaitali

[chaitalisathe]

I tried adding -suppress 2892 in verilog compilation. I was able to compile all verilog files without updating "default nettype none".

I am still facing issue with undefined FPGA outputs.