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Mininum delay value in LUT SDC

Status: Open.

#1925 In lnis-uofu/OpenFPGA;

· AndreaMazzan opened on Dec 17, 2024

Bitstream manipulation for programmable clock network

Status: Open.

#1909 In lnis-uofu/OpenFPGA;

· tangxifan opened on Nov 26, 2024

Reduce Unique Tiles in FPGA Fabric to Simplify Implementation Efforts

Status: Open.

#1903 In lnis-uofu/OpenFPGA;

· AhmadHouraniah opened on Nov 18, 2024

QL-MemoryBank-Flatten "num_wl" is ignored when "num_regions" is defined

Status: Open.

#1901 In lnis-uofu/OpenFPGA;

· mustafaarslan0 opened on Nov 18, 2024

Tileable routing architecture

Status: Open.

#1828 In lnis-uofu/OpenFPGA;

· narutozxp opened on Sep 10, 2024

Getting fanin error while trying to use custom pinlocations

Status: Open.

#1814 In lnis-uofu/OpenFPGA;

· PradyumnaG opened on Aug 30, 2024

Getting an error regarding route_chan_width

Status: Open.

#1755 In lnis-uofu/OpenFPGA;

· PradyumnaG opened on Jul 23, 2024

Bitstream updates and reconfiguration support in OpenFPGA

Status: Open.

#1723 In lnis-uofu/OpenFPGA;

· ohault opened on Jun 23, 2024

Assertion '1 == driver_switches.size()

Status: Open.

#1710 In lnis-uofu/OpenFPGA;

· kpatinos-intel opened on Jun 12, 2024

repacker seems underconstrained and fully constrained would be simpler and easier to work with

Status: Open.

#1673 In lnis-uofu/OpenFPGA;

· rs-dhow opened on May 16, 2024

repacker greatly alters one LUT in 2xLUT5 mode of an FLE in some cases when other LUT5 is unused yet configured as a wire-LUT in the .net

Status: Open.

#1672 In lnis-uofu/OpenFPGA;

· rs-dhow opened on May 16, 2024

repacker changes internal feedback path to external feedback

Status: Open.

#1671 In lnis-uofu/OpenFPGA;

· rs-dhow opened on May 16, 2024