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[llvm][AArch64] SVE2 is an optional feature in ARMv9.0a #96007

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Merged
merged 4 commits into from
Jun 20, 2024
Merged

[llvm][AArch64] SVE2 is an optional feature in ARMv9.0a #96007

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b18411c
[llvm][AArch64] SVE2 is an optional feature in ARMv9.0a
jroelofs Jun 18, 2024
93c8e15
Merge branch 'main' into jroelofs/no-automatic-defaultexts
jroelofs Jun 19, 2024
fa7e32d
Add clang and llvm release notes for the change in feature dependencies
jroelofs Jun 19, 2024
5a31a1e
clarify llvm release note. drop clang one
jroelofs Jun 20, 2024
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7 changes: 7 additions & 0 deletions llvm/docs/ReleaseNotes.rst
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Expand Up @@ -108,6 +108,13 @@ Changes to the AArch64 Backend
in ``standard`` being equal to ``bti+pac-ret+pc`` when ``+pauth-lr``
is passed as part of ``-mcpu=`` options.

* SVE and SVE2 have been moved to the default extensions list for ARMv9.0,
making them optional per the Arm ARM. Existing v9.0+ CPUs in the backend that
support these extensions continue to have these features enabled by default
when specified via ``-march=`` or an ``-mcpu=`` that supports them. The
attribute ``"target-features"="+v9a"`` no longer implies ``"+sve"`` and
``"+sve2"`` respectively.

Changes to the AMDGPU Backend
-----------------------------

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64Features.td
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Expand Up @@ -911,7 +911,7 @@ def HasV8_9aOps : Architecture64<8, 9, "a", "v8.9a",
!listconcat(HasV8_8aOps.DefaultExts, [FeatureSPECRES2, FeatureCSSC,
FeatureRASv2])>;
def HasV9_0aOps : Architecture64<9, 0, "a", "v9a",
[HasV8_5aOps, FeatureMEC, FeatureSVE2],
[HasV8_5aOps, FeatureMEC],
!listconcat(HasV8_5aOps.DefaultExts, [FeatureFullFP16, FeatureSVE,
FeatureSVE2])>;
def HasV9_1aOps : Architecture64<9, 1, "a", "v9.1a",
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36 changes: 24 additions & 12 deletions llvm/lib/Target/AArch64/AArch64Processors.td
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Expand Up @@ -690,11 +690,13 @@ def ProcessorFeatures {
list<SubtargetFeature> A520 = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
FeatureFP16FML,
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes];
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
FeatureSVE, FeatureSVE2];
list<SubtargetFeature> A520AE = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
FeatureFP16FML,
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes];
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
FeatureSVE, FeatureSVE2];
list<SubtargetFeature> A65 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
FeatureNEON, FeatureFullFP16, FeatureDotProd,
FeatureRCPC, FeatureSSBS, FeatureRAS,
Expand Down Expand Up @@ -726,19 +728,23 @@ def ProcessorFeatures {
FeatureFP16FML, FeatureSVE, FeatureTRBE,
FeatureSVE2BitPerm, FeatureBF16, FeatureETE,
FeaturePerfMon, FeatureMatMulInt8, FeatureSPE,
FeatureSB, FeatureSSBS, FeatureFullFP16, FeaturePAuth, FeaturePredRes, FeatureFlagM];
FeatureSB, FeatureSSBS, FeatureFullFP16, FeaturePAuth, FeaturePredRes, FeatureFlagM,
FeatureSVE2];
list<SubtargetFeature> A720 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
FeatureTRBE, FeatureSVE2BitPerm, FeatureETE,
FeaturePerfMon, FeatureSPE, FeatureSPE_EEF,
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes];
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
FeatureSVE, FeatureSVE2];
list<SubtargetFeature> A720AE = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
FeatureTRBE, FeatureSVE2BitPerm, FeatureETE,
FeaturePerfMon, FeatureSPE, FeatureSPE_EEF,
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes];
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
FeatureSVE, FeatureSVE2];
list<SubtargetFeature> A725 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
FeatureETE, FeaturePerfMon, FeatureSPE,
FeatureSVE2BitPerm, FeatureSPE_EEF, FeatureTRBE,
FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS];
FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS,
FeatureSVE, FeatureSVE2];
list<SubtargetFeature> R82 = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16,
FeatureFP16FML, FeatureSSBS, FeaturePredRes,
FeatureSB, FeatureRDM, FeatureDotProd,
Expand Down Expand Up @@ -771,16 +777,19 @@ def ProcessorFeatures {
FeatureSPE, FeatureBF16, FeatureMatMulInt8,
FeatureMTE, FeatureSVE2BitPerm, FeatureFullFP16,
FeatureFP16FML,
FeatureSB, FeaturePAuth, FeaturePredRes, FeatureFlagM, FeatureSSBS];
FeatureSB, FeaturePAuth, FeaturePredRes, FeatureFlagM, FeatureSSBS,
FeatureSVE2];
list<SubtargetFeature> X4 = [HasV9_2aOps,
FeaturePerfMon, FeatureETE, FeatureTRBE,
FeatureSPE, FeatureMTE, FeatureSVE2BitPerm,
FeatureFP16FML, FeatureSPE_EEF,
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes];
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
FeatureSVE, FeatureSVE2];
list<SubtargetFeature> X925 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
FeatureETE, FeaturePerfMon, FeatureSPE,
FeatureSVE2BitPerm, FeatureSPE_EEF, FeatureTRBE,
FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS];
FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS,
FeatureSVE, FeatureSVE2];
list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON,
FeatureSHA2, FeaturePerfMon, FeatureFullFP16,
FeatureSVE, FeatureComplxNum,
Expand Down Expand Up @@ -849,7 +858,8 @@ def ProcessorFeatures {
FeatureFullFP16, FeatureMTE, FeaturePerfMon,
FeatureRandGen, FeatureSPE, FeatureSPE_EEF,
FeatureSVE2BitPerm,
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM];
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM,
FeatureSVE, FeatureSVE2];
list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist,
FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureFP16FML,
FeatureFullFP16, FeatureMatMulInt8, FeatureNEON,
Expand All @@ -871,12 +881,14 @@ def ProcessorFeatures {
FeatureFullFP16, FeatureLS64, FeatureMTE,
FeaturePerfMon, FeatureRandGen, FeatureSPE,
FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE,
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM];
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM,
FeatureSVE, FeatureSVE2];
list<SubtargetFeature> NeoverseV3AE = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
FeatureFullFP16, FeatureLS64, FeatureMTE,
FeaturePerfMon, FeatureRandGen, FeatureSPE,
FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE,
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM];
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM,
FeatureSVE, FeatureSVE2];
list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
FeatureNEON, FeatureSPE, FeaturePerfMon];
list<SubtargetFeature> ThunderX = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES,
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2 changes: 1 addition & 1 deletion llvm/unittests/TargetParser/TargetParserTest.cpp
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Expand Up @@ -2474,7 +2474,7 @@ AArch64ExtensionDependenciesBaseArchTestParams
{},
{"v8.1a", "crc", "fp-armv8", "lse", "rdm", "neon"},
{}},
{AArch64::ARMV9_5A, {}, {"v9.5a", "sve", "sve2", "mops", "cpa"}, {}},
{AArch64::ARMV9_5A, {}, {"v9.5a", "mops", "cpa"}, {}},

// Positive modifiers
{AArch64::ARMV8A, {"fp16"}, {"fullfp16"}, {}},
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