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Merged
merged 7 commits into from
Jun 21, 2024
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[Clang][AArch64] Expose compatible SVE intrinsics with only +sme #95787

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b6c58b2
[Clang][AArch64] Expose compatible SVE intrinsics with only +sme
sdesmalen-arm Jun 17, 2024
880dc1b
Add RUN lines and fix up tests
sdesmalen-arm Jun 17, 2024
6a3acef
Use llvm_unreachable instead of assert
sdesmalen-arm Jun 19, 2024
79e154b
Change '(sve,bf16)|sme' to '(sve|sme),bf16'.
sdesmalen-arm Jun 19, 2024
b20b010
Fix condition for llvm_unreachable
sdesmalen-arm Jun 19, 2024
e9d652e
Update Sema tests after changing target guards
sdesmalen-arm Jun 19, 2024
4820ab0
Addres review comments
sdesmalen-arm Jun 20, 2024
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152 changes: 89 additions & 63 deletions clang/include/clang/Basic/arm_sve.td
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2 changes: 1 addition & 1 deletion clang/include/clang/Basic/arm_sve_sme_incl.td
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Original file line number Diff line number Diff line change
Expand Up @@ -272,7 +272,7 @@ class Inst<string n, string p, string t, MergeType mt, string i,
string Name = n;
string Prototype = p;
string Types = t;
string TargetGuard = "sve";
string TargetGuard = "sve|sme";
int Merge = mt.Value;
string MergeSuffix = mt.Suffix;
string LLVMIntrinsic = i;
Expand Down
140 changes: 74 additions & 66 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c
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50 changes: 29 additions & 21 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abs.c
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Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,16 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s

#include <arm_sve.h>

#if defined __ARM_FEATURE_SME
#define MODE_ATTR __arm_streaming
#else
#define MODE_ATTR
#endif

#ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
Expand All @@ -24,7 +32,7 @@
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
svint8_t test_svabs_s8_z(svbool_t pg, svint8_t op)
svint8_t test_svabs_s8_z(svbool_t pg, svint8_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_s8,_z,)(pg, op);
}
Expand All @@ -41,7 +49,7 @@ svint8_t test_svabs_s8_z(svbool_t pg, svint8_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svint16_t test_svabs_s16_z(svbool_t pg, svint16_t op)
svint16_t test_svabs_s16_z(svbool_t pg, svint16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_s16,_z,)(pg, op);
}
Expand All @@ -58,7 +66,7 @@ svint16_t test_svabs_s16_z(svbool_t pg, svint16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
svint32_t test_svabs_s32_z(svbool_t pg, svint32_t op)
svint32_t test_svabs_s32_z(svbool_t pg, svint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_s32,_z,)(pg, op);
}
Expand All @@ -75,7 +83,7 @@ svint32_t test_svabs_s32_z(svbool_t pg, svint32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
svint64_t test_svabs_s64_z(svbool_t pg, svint64_t op)
svint64_t test_svabs_s64_z(svbool_t pg, svint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_s64,_z,)(pg, op);
}
Expand All @@ -90,7 +98,7 @@ svint64_t test_svabs_s64_z(svbool_t pg, svint64_t op)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> [[INACTIVE:%.*]], <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
svint8_t test_svabs_s8_m(svint8_t inactive, svbool_t pg, svint8_t op)
svint8_t test_svabs_s8_m(svint8_t inactive, svbool_t pg, svint8_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_s8,_m,)(inactive, pg, op);
}
Expand All @@ -107,7 +115,7 @@ svint8_t test_svabs_s8_m(svint8_t inactive, svbool_t pg, svint8_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> [[INACTIVE:%.*]], <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svint16_t test_svabs_s16_m(svint16_t inactive, svbool_t pg, svint16_t op)
svint16_t test_svabs_s16_m(svint16_t inactive, svbool_t pg, svint16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_s16,_m,)(inactive, pg, op);
}
Expand All @@ -124,7 +132,7 @@ svint16_t test_svabs_s16_m(svint16_t inactive, svbool_t pg, svint16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> [[INACTIVE:%.*]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
svint32_t test_svabs_s32_m(svint32_t inactive, svbool_t pg, svint32_t op)
svint32_t test_svabs_s32_m(svint32_t inactive, svbool_t pg, svint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_s32,_m,)(inactive, pg, op);
}
Expand All @@ -141,7 +149,7 @@ svint32_t test_svabs_s32_m(svint32_t inactive, svbool_t pg, svint32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> [[INACTIVE:%.*]], <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
svint64_t test_svabs_s64_m(svint64_t inactive, svbool_t pg, svint64_t op)
svint64_t test_svabs_s64_m(svint64_t inactive, svbool_t pg, svint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_s64,_m,)(inactive, pg, op);
}
Expand All @@ -156,7 +164,7 @@ svint64_t test_svabs_s64_m(svint64_t inactive, svbool_t pg, svint64_t op)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.abs.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
svint8_t test_svabs_s8_x(svbool_t pg, svint8_t op)
svint8_t test_svabs_s8_x(svbool_t pg, svint8_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_s8,_x,)(pg, op);
}
Expand All @@ -173,7 +181,7 @@ svint8_t test_svabs_s8_x(svbool_t pg, svint8_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.abs.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svint16_t test_svabs_s16_x(svbool_t pg, svint16_t op)
svint16_t test_svabs_s16_x(svbool_t pg, svint16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_s16,_x,)(pg, op);
}
Expand All @@ -190,7 +198,7 @@ svint16_t test_svabs_s16_x(svbool_t pg, svint16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
svint32_t test_svabs_s32_x(svbool_t pg, svint32_t op)
svint32_t test_svabs_s32_x(svbool_t pg, svint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_s32,_x,)(pg, op);
}
Expand All @@ -207,7 +215,7 @@ svint32_t test_svabs_s32_x(svbool_t pg, svint32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.abs.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
svint64_t test_svabs_s64_x(svbool_t pg, svint64_t op)
svint64_t test_svabs_s64_x(svbool_t pg, svint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_s64,_x,)(pg, op);
}
Expand All @@ -224,7 +232,7 @@ svint64_t test_svabs_s64_x(svbool_t pg, svint64_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fabs.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
svfloat16_t test_svabs_f16_z(svbool_t pg, svfloat16_t op)
svfloat16_t test_svabs_f16_z(svbool_t pg, svfloat16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_f16,_z,)(pg, op);
}
Expand All @@ -241,7 +249,7 @@ svfloat16_t test_svabs_f16_z(svbool_t pg, svfloat16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fabs.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
//
svfloat32_t test_svabs_f32_z(svbool_t pg, svfloat32_t op)
svfloat32_t test_svabs_f32_z(svbool_t pg, svfloat32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_f32,_z,)(pg, op);
}
Expand All @@ -258,7 +266,7 @@ svfloat32_t test_svabs_f32_z(svbool_t pg, svfloat32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.fabs.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
//
svfloat64_t test_svabs_f64_z(svbool_t pg, svfloat64_t op)
svfloat64_t test_svabs_f64_z(svbool_t pg, svfloat64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_f64,_z,)(pg, op);
}
Expand All @@ -275,7 +283,7 @@ svfloat64_t test_svabs_f64_z(svbool_t pg, svfloat64_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fabs.nxv8f16(<vscale x 8 x half> [[INACTIVE:%.*]], <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
svfloat16_t test_svabs_f16_m(svfloat16_t inactive, svbool_t pg, svfloat16_t op)
svfloat16_t test_svabs_f16_m(svfloat16_t inactive, svbool_t pg, svfloat16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_f16,_m,)(inactive, pg, op);
}
Expand All @@ -292,7 +300,7 @@ svfloat16_t test_svabs_f16_m(svfloat16_t inactive, svbool_t pg, svfloat16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fabs.nxv4f32(<vscale x 4 x float> [[INACTIVE:%.*]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
//
svfloat32_t test_svabs_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op)
svfloat32_t test_svabs_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_f32,_m,)(inactive, pg, op);
}
Expand All @@ -309,7 +317,7 @@ svfloat32_t test_svabs_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.fabs.nxv2f64(<vscale x 2 x double> [[INACTIVE:%.*]], <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
//
svfloat64_t test_svabs_f64_m(svfloat64_t inactive, svbool_t pg, svfloat64_t op)
svfloat64_t test_svabs_f64_m(svfloat64_t inactive, svbool_t pg, svfloat64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_f64,_m,)(inactive, pg, op);
}
Expand All @@ -326,7 +334,7 @@ svfloat64_t test_svabs_f64_m(svfloat64_t inactive, svbool_t pg, svfloat64_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fabs.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
svfloat16_t test_svabs_f16_x(svbool_t pg, svfloat16_t op)
svfloat16_t test_svabs_f16_x(svbool_t pg, svfloat16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_f16,_x,)(pg, op);
}
Expand All @@ -343,7 +351,7 @@ svfloat16_t test_svabs_f16_x(svbool_t pg, svfloat16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fabs.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
//
svfloat32_t test_svabs_f32_x(svbool_t pg, svfloat32_t op)
svfloat32_t test_svabs_f32_x(svbool_t pg, svfloat32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_f32,_x,)(pg, op);
}
Expand All @@ -360,7 +368,7 @@ svfloat32_t test_svabs_f32_x(svbool_t pg, svfloat32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.fabs.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
//
svfloat64_t test_svabs_f64_x(svbool_t pg, svfloat64_t op)
svfloat64_t test_svabs_f64_x(svbool_t pg, svfloat64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svabs,_f64,_x,)(pg, op);
}
18 changes: 13 additions & 5 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acge.c
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Expand Up @@ -5,8 +5,16 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -o /dev/null %s

#include <arm_sve.h>

#if defined __ARM_FEATURE_SME
#define MODE_ATTR __arm_streaming
#else
#define MODE_ATTR
#endif

#ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
Expand All @@ -28,7 +36,7 @@
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svacge_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2)
svbool_t test_svacge_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svacge,_f16,,)(pg, op1, op2);
}
Expand All @@ -47,7 +55,7 @@ svbool_t test_svacge_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svacge_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
svbool_t test_svacge_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svacge,_f32,,)(pg, op1, op2);
}
Expand All @@ -66,7 +74,7 @@ svbool_t test_svacge_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svacge_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
svbool_t test_svacge_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svacge,_f64,,)(pg, op1, op2);
}
Expand All @@ -89,7 +97,7 @@ svbool_t test_svacge_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svacge_n_f32(svbool_t pg, svfloat32_t op1, float32_t op2)
svbool_t test_svacge_n_f32(svbool_t pg, svfloat32_t op1, float32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svacge,_n_f32,,)(pg, op1, op2);
}
Expand All @@ -112,7 +120,7 @@ svbool_t test_svacge_n_f32(svbool_t pg, svfloat32_t op1, float32_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svacge_n_f64(svbool_t pg, svfloat64_t op1, float64_t op2)
svbool_t test_svacge_n_f64(svbool_t pg, svfloat64_t op1, float64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svacge,_n_f64,,)(pg, op1, op2);
}
18 changes: 13 additions & 5 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acgt.c
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Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,16 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -o /dev/null %s

#include <arm_sve.h>

#if defined __ARM_FEATURE_SME
#define MODE_ATTR __arm_streaming
#else
#define MODE_ATTR
#endif

#ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
Expand All @@ -28,7 +36,7 @@
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svacgt_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2)
svbool_t test_svacgt_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svacgt,_f16,,)(pg, op1, op2);
}
Expand All @@ -47,7 +55,7 @@ svbool_t test_svacgt_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svacgt_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
svbool_t test_svacgt_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svacgt,_f32,,)(pg, op1, op2);
}
Expand All @@ -66,7 +74,7 @@ svbool_t test_svacgt_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svacgt_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
svbool_t test_svacgt_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svacgt,_f64,,)(pg, op1, op2);
}
Expand All @@ -89,7 +97,7 @@ svbool_t test_svacgt_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svacgt_n_f32(svbool_t pg, svfloat32_t op1, float32_t op2)
svbool_t test_svacgt_n_f32(svbool_t pg, svfloat32_t op1, float32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svacgt,_n_f32,,)(pg, op1, op2);
}
Expand All @@ -112,7 +120,7 @@ svbool_t test_svacgt_n_f32(svbool_t pg, svfloat32_t op1, float32_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svacgt_n_f64(svbool_t pg, svfloat64_t op1, float64_t op2)
svbool_t test_svacgt_n_f64(svbool_t pg, svfloat64_t op1, float64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svacgt,_n_f64,,)(pg, op1, op2);
}
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