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[WebAssembly] Implement prototype f32.load_f16 instruction. #90906

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merged 3 commits into from
May 7, 2024
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[WebAssembly] Implement prototype f32.load_f16 instruction. #90906

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14313fa
[WebAssembly] Implement prototype f32.load_f16 instruction.
brendandahl May 1, 2024
aa8b37a
Use short for builtin. Alternatively we could use _Float16, but then
brendandahl May 2, 2024
e3e90b5
Review comments.
brendandahl May 6, 2024
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3 changes: 3 additions & 0 deletions clang/include/clang/Basic/BuiltinsWebAssembly.def
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Expand Up @@ -190,6 +190,9 @@ TARGET_BUILTIN(__builtin_wasm_relaxed_dot_i8x16_i7x16_s_i16x8, "V8sV16ScV16Sc",
TARGET_BUILTIN(__builtin_wasm_relaxed_dot_i8x16_i7x16_add_s_i32x4, "V4iV16ScV16ScV4i", "nc", "relaxed-simd")
TARGET_BUILTIN(__builtin_wasm_relaxed_dot_bf16x8_add_f32_f32x4, "V4fV8UsV8UsV4f", "nc", "relaxed-simd")

// Half-Precision (fp16)
TARGET_BUILTIN(__builtin_wasm_loadf16_f32, "fh*", "nU", "half-precision")

// Reference Types builtins
// Some builtins are custom type-checked - see 't' as part of the third argument,
// in which case the argument spec (second argument) is unused.
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5 changes: 5 additions & 0 deletions clang/lib/CodeGen/CGBuiltin.cpp
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Expand Up @@ -21257,6 +21257,11 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
CGM.getIntrinsic(Intrinsic::wasm_relaxed_dot_bf16x8_add_f32);
return Builder.CreateCall(Callee, {LHS, RHS, Acc});
}
case WebAssembly::BI__builtin_wasm_loadf16_f32: {
Value *Addr = EmitScalarExpr(E->getArg(0));
Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_loadf16_f32);
return Builder.CreateCall(Callee, {Addr});
}
case WebAssembly::BI__builtin_wasm_table_get: {
assert(E->getArg(0)->getType()->isArrayType());
Value *Table = EmitArrayToPointerDecay(E->getArg(0)).emitRawPointer(*this);
Expand Down
9 changes: 7 additions & 2 deletions clang/test/CodeGen/builtins-wasm.c
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@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple wasm32-unknown-unknown -target-feature +reference-types -target-feature +simd128 -target-feature +relaxed-simd -target-feature +nontrapping-fptoint -target-feature +exception-handling -target-feature +bulk-memory -target-feature +atomics -flax-vector-conversions=none -O3 -emit-llvm -o - %s | FileCheck %s -check-prefixes WEBASSEMBLY,WEBASSEMBLY32
// RUN: %clang_cc1 -triple wasm64-unknown-unknown -target-feature +reference-types -target-feature +simd128 -target-feature +relaxed-simd -target-feature +nontrapping-fptoint -target-feature +exception-handling -target-feature +bulk-memory -target-feature +atomics -flax-vector-conversions=none -O3 -emit-llvm -o - %s | FileCheck %s -check-prefixes WEBASSEMBLY,WEBASSEMBLY64
// RUN: %clang_cc1 -triple wasm32-unknown-unknown -target-feature +reference-types -target-feature +simd128 -target-feature +relaxed-simd -target-feature +nontrapping-fptoint -target-feature +exception-handling -target-feature +bulk-memory -target-feature +atomics -target-feature +half-precision -flax-vector-conversions=none -O3 -emit-llvm -o - %s | FileCheck %s -check-prefixes WEBASSEMBLY,WEBASSEMBLY32
// RUN: %clang_cc1 -triple wasm64-unknown-unknown -target-feature +reference-types -target-feature +simd128 -target-feature +relaxed-simd -target-feature +nontrapping-fptoint -target-feature +exception-handling -target-feature +bulk-memory -target-feature +atomics -target-feature +half-precision -flax-vector-conversions=none -O3 -emit-llvm -o - %s | FileCheck %s -check-prefixes WEBASSEMBLY,WEBASSEMBLY64
// RUN: not %clang_cc1 -triple wasm64-unknown-unknown -target-feature +reference-types -target-feature +nontrapping-fptoint -target-feature +exception-handling -target-feature +bulk-memory -target-feature +atomics -flax-vector-conversions=none -O3 -emit-llvm -o - %s 2>&1 | FileCheck %s -check-prefixes MISSING-SIMD

// SIMD convenience types
Expand Down Expand Up @@ -802,6 +802,11 @@ f32x4 relaxed_dot_bf16x8_add_f32_f32x4(u16x8 a, u16x8 b, f32x4 c) {
// WEBASSEMBLY-NEXT: ret
}

float load_f16_f32(__fp16 *addr) {
return __builtin_wasm_loadf16_f32(addr);
// WEBASSEMBLY: call float @llvm.wasm.loadf16.f32(ptr %{{.*}})
}

__externref_t externref_null() {
return __builtin_wasm_ref_null_extern();
// WEBASSEMBLY: tail call ptr addrspace(10) @llvm.wasm.ref.null.extern()
Expand Down
12 changes: 12 additions & 0 deletions llvm/include/llvm/IR/IntrinsicsWebAssembly.td
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Expand Up @@ -321,6 +321,18 @@ def int_wasm_relaxed_dot_bf16x8_add_f32:
[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4f32_ty],
[IntrNoMem, IntrSpeculatable]>;

//===----------------------------------------------------------------------===//
// Half-precision intrinsics (experimental)
//===----------------------------------------------------------------------===//

// TODO: Replace these intrinsic with normal ISel patterns once the XXX
// instructions are merged to the proposal.
def int_wasm_loadf16_f32:
Intrinsic<[llvm_float_ty],
[llvm_ptr_ty],
[IntrReadMem, IntrArgMemOnly],
"", [SDNPMemOperand]>;


//===----------------------------------------------------------------------===//
// Thread-local storage intrinsics
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1 change: 1 addition & 0 deletions llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
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Expand Up @@ -206,6 +206,7 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
WASM_LOAD_STORE(LOAD16_SPLAT)
WASM_LOAD_STORE(LOAD_LANE_I16x8)
WASM_LOAD_STORE(STORE_LANE_I16x8)
WASM_LOAD_STORE(LOAD_F16_F32)
return 1;
WASM_LOAD_STORE(LOAD_I32)
WASM_LOAD_STORE(LOAD_F32)
Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
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Expand Up @@ -906,6 +906,14 @@ bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
Info.align = Align(8);
Info.flags = MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad;
return true;
case Intrinsic::wasm_loadf16_f32:
Info.opc = ISD::INTRINSIC_W_CHAIN;
Info.memVT = MVT::f16;
Info.ptrVal = I.getArgOperand(0);
Info.offset = 0;
Info.align = Align(2);
Info.flags = MachineMemOperand::MOLoad;
return true;
default:
return false;
}
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5 changes: 5 additions & 0 deletions llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td
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Expand Up @@ -72,6 +72,9 @@ defm LOAD16_U_I64 : WebAssemblyLoad<I64, "i64.load16_u", 0x33, []>;
defm LOAD32_S_I64 : WebAssemblyLoad<I64, "i64.load32_s", 0x34, []>;
defm LOAD32_U_I64 : WebAssemblyLoad<I64, "i64.load32_u", 0x35, []>;

// Half Precision
defm LOAD_F16_F32 : WebAssemblyLoad<F32, "f32.load_f16", 0xfc30, [HasHalfPrecision]>;

// Pattern matching

multiclass LoadPat<ValueType ty, SDPatternOperator kind, string Name> {
Expand Down Expand Up @@ -111,6 +114,8 @@ defm : LoadPat<i64, extloadi8, "LOAD8_U_I64">;
defm : LoadPat<i64, extloadi16, "LOAD16_U_I64">;
defm : LoadPat<i64, extloadi32, "LOAD32_U_I64">;

defm : LoadPat<f32, int_wasm_loadf16_f32, "LOAD_F16_F32">;

// Defines atomic and non-atomic stores, regular and truncating
multiclass WebAssemblyStore<WebAssemblyRegClass rc, string Name, int Opcode,
list<Predicate> reqs = []> {
Expand Down
12 changes: 12 additions & 0 deletions llvm/test/CodeGen/WebAssembly/half-precision.ll
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@@ -0,0 +1,12 @@
; RUN: llc < %s --mtriple=wasm32-unknown-unknown -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+half-precision | FileCheck %s
; RUN: llc < %s --mtriple=wasm64-unknown-unknown -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+half-precision | FileCheck %s

declare float @llvm.wasm.loadf32.f16(ptr)

; CHECK-LABEL: ldf16_32:
; CHECK: f32.load_f16 $push[[NUM0:[0-9]+]]=, 0($0){{$}}
; CHECK-NEXT: return $pop[[NUM0]]{{$}}
define float @ldf16_32(ptr %p) {
%v = call float @llvm.wasm.loadf16.f32(ptr %p)
ret float %v
}
28 changes: 27 additions & 1 deletion llvm/test/CodeGen/WebAssembly/offset.ll
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@@ -1,4 +1,4 @@
; RUN: llc < %s -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers -disable-wasm-fallthrough-return-opt | FileCheck %s
; RUN: llc < %s -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers -disable-wasm-fallthrough-return-opt -mattr=+half-precision | FileCheck %s

; Test constant load and store address offsets.

Expand Down Expand Up @@ -666,3 +666,29 @@ define {i32,i32,i32,i32} @aggregate_return() {
define {i64,i32,i16,i8} @aggregate_return_without_merge() {
ret {i64,i32,i16,i8} zeroinitializer
}

;===----------------------------------------------------------------------------
; Loads: Half Precision
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I didn't add many tests here, since it seems pretty well covered for other load patters.

;===----------------------------------------------------------------------------

; Fold an offset into a zero-extending load.

; CHECK-LABEL: load_f16_f32_with_folded_offset:
; CHECK: f32.load_f16 $push0=, 24($0){{$}}
define float @load_f16_f32_with_folded_offset(ptr %p) {
%q = ptrtoint ptr %p to i32
%r = add nuw i32 %q, 24
%s = inttoptr i32 %r to ptr
%t = call float @llvm.wasm.loadf16.f32(ptr %s)
ret float %t
}

; Fold a gep offset into a zero-extending load.

; CHECK-LABEL: load_f16_f32_with_folded_gep_offset:
; CHECK: f32.load_f16 $push0=, 24($0){{$}}
define float @load_f16_f32_with_folded_gep_offset(ptr %p) {
%s = getelementptr inbounds i8, ptr %p, i32 24
%t = call float @llvm.wasm.loadf16.f32(ptr %s)
ret float %t
}
5 changes: 4 additions & 1 deletion llvm/test/MC/WebAssembly/simd-encodings.s
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@@ -1,4 +1,4 @@
# RUN: llvm-mc -no-type-check -show-encoding -triple=wasm32-unknown-unknown -mattr=+simd128,+relaxed-simd < %s | FileCheck %s
# RUN: llvm-mc -no-type-check -show-encoding -triple=wasm32-unknown-unknown -mattr=+simd128,+relaxed-simd,+half-precision < %s | FileCheck %s

main:
.functype main () -> ()
Expand Down Expand Up @@ -839,4 +839,7 @@ main:
# CHECK: i32x4.relaxed_dot_i8x16_i7x16_add_s # encoding: [0xfd,0x93,0x02]
i32x4.relaxed_dot_i8x16_i7x16_add_s

# CHECK: f32.load_f16 48 # encoding: [0xfc,0x30,0x01,0x30]
f32.load_f16 48

end_function
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