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[RISCV] Support interleaved accesses for scalable vector. #90583

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Merged
merged 2 commits into from
May 3, 2024
Merged

[RISCV] Support interleaved accesses for scalable vector. #90583

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96efe54
[RISCV] Support interleaved accesses for scalable vector.
Mel-Chen Apr 30, 2024
7ced0be
Add the RUN command for test case that shows the default choice
Mel-Chen May 3, 2024
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29 changes: 18 additions & 11 deletions llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -599,37 +599,44 @@ InstructionCost RISCVTTIImpl::getInterleavedMemoryOpCost(
unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
bool UseMaskForCond, bool UseMaskForGaps) {
if (isa<ScalableVectorType>(VecTy))
if (isa<ScalableVectorType>(VecTy) && Factor != 2)
return InstructionCost::getInvalid();
auto *FVTy = cast<FixedVectorType>(VecTy);
InstructionCost MemCost =
getMemoryOpCost(Opcode, VecTy, Alignment, AddressSpace, CostKind);
unsigned VF = FVTy->getNumElements() / Factor;

// The interleaved memory access pass will lower interleaved memory ops (i.e
// a load and store followed by a specific shuffle) to vlseg/vsseg
// intrinsics. In those cases then we can treat it as if it's just one (legal)
// memory op
if (!UseMaskForCond && !UseMaskForGaps &&
Factor <= TLI->getMaxSupportedInterleaveFactor()) {
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(FVTy);
auto *VTy = cast<VectorType>(VecTy);
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(VTy);
// Need to make sure type has't been scalarized
if (LT.second.isFixedLengthVector()) {
auto *LegalFVTy = FixedVectorType::get(FVTy->getElementType(),
LT.second.getVectorNumElements());
if (LT.second.isVector()) {
auto *LegalVTy = VectorType::get(VTy->getElementType(),
LT.second.getVectorElementCount());
// FIXME: We use the memory op cost of the *legalized* type here, becuase
// it's getMemoryOpCost returns a really expensive cost for types like
// <6 x i8>, which show up when doing interleaves of Factor=3 etc.
// Should the memory op cost of these be cheaper?
if (TLI->isLegalInterleavedAccessType(LegalFVTy, Factor, Alignment,
if (TLI->isLegalInterleavedAccessType(LegalVTy, Factor, Alignment,
AddressSpace, DL)) {
InstructionCost LegalMemCost = getMemoryOpCost(
Opcode, LegalFVTy, Alignment, AddressSpace, CostKind);
Opcode, LegalVTy, Alignment, AddressSpace, CostKind);
return LT.first + LegalMemCost;
}
}
}

// TODO: Return the cost of interleaved accesses for scalable vector when
// unable to convert to segment accesses instructions.
if (isa<ScalableVectorType>(VecTy))
return InstructionCost::getInvalid();

auto *FVTy = cast<FixedVectorType>(VecTy);
InstructionCost MemCost =
getMemoryOpCost(Opcode, VecTy, Alignment, AddressSpace, CostKind);
unsigned VF = FVTy->getNumElements() / Factor;

// An interleaved load will look like this for Factor=3:
// %wide.vec = load <12 x i32>, ptr %3, align 4
// %strided.vec = shufflevector %wide.vec, poison, <4 x i32> <stride mask>
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