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[RISCV] Use RISCVISD::SHL_ADD in transformAddShlImm #89832

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Merged
merged 2 commits into from
May 13, 2024
Merged

[RISCV] Use RISCVISD::SHL_ADD in transformAddShlImm #89832

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[RISCV] Use RISCVISD::SHL_ADD in transformAddShlImm [NFC]
preames Apr 18, 2024
f54889a
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preames Apr 23, 2024
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18 changes: 10 additions & 8 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -12817,10 +12817,9 @@ static SDValue transformAddShlImm(SDNode *N, SelectionDAG &DAG,
SDLoc DL(N);
SDValue NS = (C0 < C1) ? N0->getOperand(0) : N1->getOperand(0);
SDValue NL = (C0 > C1) ? N0->getOperand(0) : N1->getOperand(0);
SDValue NA0 =
DAG.getNode(ISD::SHL, DL, VT, NL, DAG.getConstant(Diff, DL, VT));
SDValue NA1 = DAG.getNode(ISD::ADD, DL, VT, NA0, NS);
return DAG.getNode(ISD::SHL, DL, VT, NA1, DAG.getConstant(Bits, DL, VT));
SDValue SHADD = DAG.getNode(RISCVISD::SHL_ADD, DL, VT, NL,
DAG.getConstant(Diff, DL, VT), NS);
return DAG.getNode(ISD::SHL, DL, VT, SHADD, DAG.getConstant(Bits, DL, VT));
}

// Combine a constant select operand into its use:
Expand Down Expand Up @@ -13056,14 +13055,17 @@ static SDValue combineAddOfBooleanXor(SDNode *N, SelectionDAG &DAG) {
N0.getOperand(0));
}

static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
static SDValue performADDCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
const RISCVSubtarget &Subtarget) {
SelectionDAG &DAG = DCI.DAG;
if (SDValue V = combineAddOfBooleanXor(N, DAG))
return V;
if (SDValue V = transformAddImmMulImm(N, DAG, Subtarget))
return V;
if (SDValue V = transformAddShlImm(N, DAG, Subtarget))
return V;
if (!DCI.isBeforeLegalize() && !DCI.isCalledByLegalizer())
if (SDValue V = transformAddShlImm(N, DAG, Subtarget))
return V;
if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget))
return V;
if (SDValue V = combineBinOpOfExtractToReduceTree(N, DAG, Subtarget))
Expand Down Expand Up @@ -16027,7 +16029,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return V;
if (SDValue V = combineToVWMACC(N, DAG, Subtarget))
return V;
return performADDCombine(N, DAG, Subtarget);
return performADDCombine(N, DCI, Subtarget);
}
case ISD::SUB: {
if (SDValue V = combineBinOp_VLToVWBinOp_VL(N, DCI, Subtarget))
Expand Down
26 changes: 26 additions & 0 deletions llvm/test/CodeGen/RISCV/addimm-mulimm.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -898,3 +898,29 @@ define i1 @pr53831(i32 %x) {
%tmp5 = icmp eq i32 %tmp4, %tmp2
ret i1 %tmp5
}

define i64 @sh2add_uw(i64 signext %0, i32 signext %1) {
; RV32IMB-LABEL: sh2add_uw:
; RV32IMB: # %bb.0: # %entry
; RV32IMB-NEXT: srli a3, a2, 27
; RV32IMB-NEXT: slli a2, a2, 5
; RV32IMB-NEXT: srli a4, a0, 29
; RV32IMB-NEXT: sh3add a1, a1, a4
; RV32IMB-NEXT: sh3add a0, a0, a2
; RV32IMB-NEXT: sltu a2, a0, a2
; RV32IMB-NEXT: add a1, a3, a1
; RV32IMB-NEXT: add a1, a1, a2
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: sh2add_uw:
; RV64IMB: # %bb.0: # %entry
; RV64IMB-NEXT: sh2add.uw a0, a1, a0
; RV64IMB-NEXT: slli a0, a0, 3
; RV64IMB-NEXT: ret
entry:
%2 = zext i32 %1 to i64
%3 = shl i64 %2, 5
%4 = shl i64 %0, 3
%5 = add i64 %3, %4
ret i64 %5
}