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[RISCV][llvm-mca] Use Sched*MC for Zvk MC instructions and add Zvk tests for P600 #89256

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[RISCV][llvm-mca] Use Sched*MC for Zvk MC instructions and add Zvk tests for P600 #89256

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205b7d3
[RISCV] Use Sched*MC for Zvk MC instructions
michaelmaitland Apr 18, 2024
f27c8d6
[RISCV][llvm-mca] Add vector crypto llvm-mca tests for P600
michaelmaitland Apr 16, 2024
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52 changes: 33 additions & 19 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
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Original file line number Diff line number Diff line change
Expand Up @@ -24,11 +24,9 @@ def tuimm5 : RISCVOp, TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
multiclass VCLMUL_MV_V_X<string opcodestr, bits<6> funct6> {
def V : VALUVV<funct6, OPMVV, opcodestr # "." # "vv">,
Sched<[WriteVIALUV_WorstCase, ReadVIALUV_WorstCase,
ReadVIALUV_WorstCase, ReadVMask]>;
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
def X : VALUVX<funct6, OPMVX, opcodestr # "." # "vx">,
Sched<[WriteVIALUX_WorstCase, ReadVIALUV_WorstCase,
ReadVIALUX_WorstCase, ReadVMask]>;
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
}

class RVInstIVI_VROR<bits<6> funct6, dag outs, dag ins, string opcodestr,
Expand Down Expand Up @@ -57,8 +55,7 @@ multiclass VROR_IV_V_X_I<string opcodestr, bits<6> funct6>
def I : RVInstIVI_VROR<funct6, (outs VR:$vd),
(ins VR:$vs2, uimm6:$imm, VMaskOp:$vm),
opcodestr # ".vi", "$vd, $vs2, $imm$vm">,
Sched<[WriteVIALUI_WorstCase, ReadVIALUV_WorstCase,
ReadVMask]>;
SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">;
}

// op vd, vs2, vs1
Expand Down Expand Up @@ -109,9 +106,11 @@ class PALUVs2NoVmBinary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
RISCVVFormat opv, string opcodestr> {
let RVVConstraint = NoConstraint in
def NAME # _VV : PALUVs2NoVmBinary<funct6_vv, vs1, opv, opcodestr # ".vv">;
def NAME # _VV : PALUVs2NoVmBinary<funct6_vv, vs1, opv, opcodestr # ".vv">,
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
let RVVConstraint = VS2Constraint in
def NAME # _VS : PALUVs2NoVmBinary<funct6_vs, vs1, opv, opcodestr # ".vs">;
def NAME # _VS : PALUVs2NoVmBinary<funct6_vs, vs1, opv, opcodestr # ".vs">,
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0

Expand Down Expand Up @@ -142,36 +141,51 @@ let Predicates = [HasStdExtZvkb] in {
} // Predicates = [HasStdExtZvkb]

let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in {
def VGHSH_VV : PALUVVNoVmTernary<0b101100, OPMVV, "vghsh.vv">;
def VGMUL_VV : PALUVs2NoVmBinary<0b101000, 0b10001, OPMVV, "vgmul.vv">;
def VGHSH_VV : PALUVVNoVmTernary<0b101100, OPMVV, "vghsh.vv">,
SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
"ReadVIALUV">;
def VGMUL_VV : PALUVs2NoVmBinary<0b101000, 0b10001, OPMVV, "vgmul.vv">,
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
} // Predicates = [HasStdExtZvkg]

let Predicates = [HasStdExtZvknhaOrZvknhb], RVVConstraint = Sha2Constraint in {
def VSHA2CH_VV : PALUVVNoVmTernary<0b101110, OPMVV, "vsha2ch.vv">;
def VSHA2CL_VV : PALUVVNoVmTernary<0b101111, OPMVV, "vsha2cl.vv">;
def VSHA2MS_VV : PALUVVNoVmTernary<0b101101, OPMVV, "vsha2ms.vv">;
def VSHA2CH_VV : PALUVVNoVmTernary<0b101110, OPMVV, "vsha2ch.vv">,
SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
"ReadVIALUV">;
def VSHA2CL_VV : PALUVVNoVmTernary<0b101111, OPMVV, "vsha2cl.vv">,
SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
"ReadVIALUV">;
def VSHA2MS_VV : PALUVVNoVmTernary<0b101101, OPMVV, "vsha2ms.vv">,
SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
"ReadVIALUV">;
} // Predicates = [HasStdExtZvknhaOrZvknhb]

let Predicates = [HasStdExtZvkned] in {
defm VAESDF : VAES_MV_V_S<0b101000, 0b101001, 0b00001, OPMVV, "vaesdf">;
defm VAESDM : VAES_MV_V_S<0b101000, 0b101001, 0b00000, OPMVV, "vaesdm">;
defm VAESEF : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">;
defm VAESEM : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;
def VAESKF1_VI : PALUVINoVm<0b100010, "vaeskf1.vi", uimm5>;
def VAESKF2_VI : PALUVINoVmBinary<0b101010, "vaeskf2.vi", uimm5>;
def VAESKF1_VI : PALUVINoVm<0b100010, "vaeskf1.vi", uimm5>,
SchedUnaryMC<"WriteVIALUV", "ReadVIALUV">;
def VAESKF2_VI : PALUVINoVmBinary<0b101010, "vaeskf2.vi", uimm5>,
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
let RVVConstraint = VS2Constraint in
def VAESZ_VS : PALUVs2NoVmBinary<0b101001, 0b00111, OPMVV, "vaesz.vs">;
def VAESZ_VS : PALUVs2NoVmBinary<0b101001, 0b00111, OPMVV, "vaesz.vs">,
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
} // Predicates = [HasStdExtZvkned]

let Predicates = [HasStdExtZvksed] in {
let RVVConstraint = NoConstraint in
def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", uimm5>;
def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", uimm5>,
SchedUnaryMC<"WriteVIALUV", "ReadVIALUV">;
defm VSM4R : VAES_MV_V_S<0b101000, 0b101001, 0b10000, OPMVV, "vsm4r">;
} // Predicates = [HasStdExtZvksed]

let Predicates = [HasStdExtZvksh], RVVConstraint = VS2Constraint in {
def VSM3C_VI : PALUVINoVmBinary<0b101011, "vsm3c.vi", uimm5>;
def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">;
def VSM3C_VI : PALUVINoVmBinary<0b101011, "vsm3c.vi", uimm5>,
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">,
SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">;
} // Predicates = [HasStdExtZvksh]

//===----------------------------------------------------------------------===//
Expand Down
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