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[RISCV] Add a MIR pass to reassociate shXadd, add, and slli to form more shXadd. #87544
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,170 @@ | ||
| //===- RISCVOptZba.cpp - MI Zba instruction optimizations -----------------===// | ||
| // | ||
| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||
| // See https://llvm.org/LICENSE.txt for license information. | ||
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
| // | ||
| //===---------------------------------------------------------------------===// | ||
| // | ||
| // This pass reassociates expressions like | ||
| // (sh3add Z, (add X, (slli Y, 5))) | ||
| // To | ||
| // (sh3add (sh2add Y, Z), X) | ||
| // | ||
| // If the shift amount is small enough. The outer shXadd keeps its original | ||
| // opcode. The inner shXadd shift amount is the difference between the slli | ||
| // shift amount and the outer shXadd shift amount. | ||
| // | ||
| // This pattern can appear when indexing a two dimensional array, but it is not | ||
| // limited to that. | ||
| // | ||
| // TODO: We can also support slli.uw by using shXadd.uw for the inner shXadd. | ||
| // TODO: This can be generalized to deeper expressions. | ||
| // | ||
| //===---------------------------------------------------------------------===// | ||
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| #include "RISCV.h" | ||
| #include "RISCVSubtarget.h" | ||
| #include "llvm/CodeGen/MachineFunctionPass.h" | ||
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| using namespace llvm; | ||
|
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| #define DEBUG_TYPE "riscv-opt-zba" | ||
| #define RISCV_OPT_ZBA_NAME "RISC-V Optimize Zba" | ||
|
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||
| namespace { | ||
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| class RISCVOptZba : public MachineFunctionPass { | ||
| public: | ||
| static char ID; | ||
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| RISCVOptZba() : MachineFunctionPass(ID) {} | ||
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| bool runOnMachineFunction(MachineFunction &MF) override; | ||
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| void getAnalysisUsage(AnalysisUsage &AU) const override { | ||
| AU.setPreservesCFG(); | ||
| MachineFunctionPass::getAnalysisUsage(AU); | ||
| } | ||
|
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| StringRef getPassName() const override { return RISCV_OPT_ZBA_NAME; } | ||
| }; | ||
|
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| } // end anonymous namespace | ||
|
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| char RISCVOptZba::ID = 0; | ||
| INITIALIZE_PASS(RISCVOptZba, DEBUG_TYPE, RISCV_OPT_ZBA_NAME, false, false) | ||
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| FunctionPass *llvm::createRISCVOptZbaPass() { return new RISCVOptZba(); } | ||
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| static MachineInstr *findShift(Register Reg, const MachineBasicBlock &MBB, | ||
| MachineRegisterInfo &MRI) { | ||
| if (!Reg.isVirtual()) | ||
| return nullptr; | ||
|
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| MachineInstr *Shift = MRI.getVRegDef(Reg); | ||
| if (!Shift || Shift->getOpcode() != RISCV::SLLI || | ||
| Shift->getParent() != &MBB || !MRI.hasOneNonDBGUse(Reg)) | ||
| return nullptr; | ||
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| return Shift; | ||
| } | ||
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| bool RISCVOptZba::runOnMachineFunction(MachineFunction &MF) { | ||
| if (skipFunction(MF.getFunction())) | ||
| return false; | ||
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| MachineRegisterInfo &MRI = MF.getRegInfo(); | ||
| const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); | ||
| const RISCVInstrInfo &TII = *ST.getInstrInfo(); | ||
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| if (!ST.hasStdExtZba()) | ||
| return false; | ||
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| bool MadeChange = true; | ||
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| for (MachineBasicBlock &MBB : MF) { | ||
| for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) { | ||
| unsigned OuterShiftAmt; | ||
| switch (MI.getOpcode()) { | ||
| default: | ||
| continue; | ||
| case RISCV::SH1ADD: | ||
| OuterShiftAmt = 1; | ||
| break; | ||
| case RISCV::SH2ADD: | ||
| OuterShiftAmt = 2; | ||
| break; | ||
| case RISCV::SH3ADD: | ||
| OuterShiftAmt = 3; | ||
| break; | ||
| } | ||
|
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| // Second operand must be virtual. | ||
| Register UnshiftedReg = MI.getOperand(2).getReg(); | ||
| if (!UnshiftedReg.isVirtual()) | ||
| continue; | ||
|
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| MachineInstr *Add = MRI.getVRegDef(UnshiftedReg); | ||
| if (!Add || Add->getOpcode() != RISCV::ADD || Add->getParent() != &MBB || | ||
| !MRI.hasOneNonDBGUse(UnshiftedReg)) | ||
| continue; | ||
|
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| Register AddReg0 = Add->getOperand(1).getReg(); | ||
| Register AddReg1 = Add->getOperand(2).getReg(); | ||
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| MachineInstr *InnerShift; | ||
| Register X; | ||
| if ((InnerShift = findShift(AddReg0, MBB, MRI))) | ||
| X = AddReg1; | ||
| else if ((InnerShift = findShift(AddReg1, MBB, MRI))) | ||
| X = AddReg0; | ||
| else | ||
| continue; | ||
|
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| unsigned InnerShiftAmt = InnerShift->getOperand(2).getImm(); | ||
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| // The inner shift amount must be at least as large as the outer shift | ||
| // amount. | ||
| if (OuterShiftAmt > InnerShiftAmt) | ||
| continue; | ||
|
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| unsigned InnerOpc; | ||
| switch (InnerShiftAmt - OuterShiftAmt) { | ||
| default: | ||
| continue; | ||
| case 0: | ||
| InnerOpc = RISCV::ADD; | ||
| break; | ||
| case 1: | ||
| InnerOpc = RISCV::SH1ADD; | ||
| break; | ||
| case 2: | ||
| InnerOpc = RISCV::SH2ADD; | ||
| break; | ||
| case 3: | ||
| InnerOpc = RISCV::SH3ADD; | ||
| break; | ||
| } | ||
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| Register Y = InnerShift->getOperand(1).getReg(); | ||
| Register Z = MI.getOperand(1).getReg(); | ||
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| Register NewReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); | ||
| BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(InnerOpc), NewReg) | ||
| .addReg(Y) | ||
| .addReg(Z); | ||
| BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(MI.getOpcode()), | ||
| MI.getOperand(0).getReg()) | ||
| .addReg(NewReg) | ||
| .addReg(X); | ||
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| MI.eraseFromParent(); | ||
| Add->eraseFromParent(); | ||
| InnerShift->eraseFromParent(); | ||
| MadeChange = true; | ||
| } | ||
| } | ||
|
|
||
| return MadeChange; | ||
| } | ||
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I think we can still reassociate this, but that can be a separate patch. :)
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That would have to be a different reassociation of some kind. Do you have an example?