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AMDGPU: Use PseudoInstr to name SIMCInstr for DSDIR and SOPs, NFC #87537

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Merged
merged 1 commit into from
Apr 3, 2024
Merged

AMDGPU: Use PseudoInstr to name SIMCInstr for DSDIR and SOPs, NFC #87537

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/DSDIRInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -112,7 +112,7 @@ class DSDIR_Real<DSDIR_Pseudo lds, dag ins, string asm, int subtarget> :
lds.Mnemonic # asm,
ins,
lds.is_direct>,
SIMCInstr <lds.Mnemonic, subtarget> {
SIMCInstr <lds.PseudoInstr, subtarget> {
let isPseudo = 0;
let isCodeGenOnly = 0;

Expand Down
78 changes: 39 additions & 39 deletions llvm/lib/Target/AMDGPU/SOPInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1972,30 +1972,30 @@ class Select_gfx6_gfx7<string opName> : SIMCInstr<opName, SIEncodingFamily.SI> {
multiclass SOP1_Real_gfx11<bits<8> op, string name = !tolower(NAME)> {
defvar ps = !cast<SOP1_Pseudo>(NAME);
def _gfx11 : SOP1_Real<op, ps, name>,
Select_gfx11<ps.Mnemonic>;
Select_gfx11<ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX11Only]>;
}

multiclass SOP1_Real_gfx12<bits<8> op, string name = !tolower(NAME)> {
defvar ps = !cast<SOP1_Pseudo>(NAME);
def _gfx12 : SOP1_Real<op, ps, name>,
Select_gfx12<ps.Mnemonic>;
Select_gfx12<ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>;
}

multiclass SOP1_M0_Real_gfx12<bits<8> op> {
def _gfx12 : SOP1_Real<op, !cast<SOP1_Pseudo>(NAME)>,
Select_gfx12<!cast<SOP1_Pseudo>(NAME).Mnemonic> {
Select_gfx12<!cast<SOP1_Pseudo>(NAME).PseudoInstr> {
let Inst{7-0} = M0_gfx11plus.HWEncoding{7-0}; // Set Src0 encoding to M0
}
}

multiclass SOP1_IMM_Real_gfx12<bits<8> op> {
defvar ps = !cast<SOP1_Pseudo>(NAME);
def _gfx12 : SOP1_Real<op, ps>,
Select_gfx12<ps.Mnemonic>;
Select_gfx12<ps.PseudoInstr>;
}

multiclass SOP1_Real_gfx11_gfx12<bits<8> op, string name = !tolower(NAME)> :
Expand Down Expand Up @@ -2106,7 +2106,7 @@ defm S_RNDNE_F16 : SOP1_Real_gfx11_gfx12<0x06e>;
multiclass SOP1_Real_gfx10<bits<8> op> {
defvar ps = !cast<SOP1_Pseudo>(NAME);
def _gfx10 : SOP1_Real<op, ps>,
Select_gfx10<ps.Mnemonic>;
Select_gfx10<ps.PseudoInstr>;
}

multiclass SOP1_Real_gfx10_gfx11_gfx12<bits<8> op> :
Expand Down Expand Up @@ -2139,7 +2139,7 @@ defm S_MOVRELSD_2_B32 : SOP1_Real_gfx10<0x049>;
multiclass SOP1_Real_gfx6_gfx7<bits<8> op> {
defvar ps = !cast<SOP1_Pseudo>(NAME);
def _gfx6_gfx7 : SOP1_Real<op, ps>,
Select_gfx6_gfx7<ps.Mnemonic>;
Select_gfx6_gfx7<ps.PseudoInstr>;
}

multiclass SOP1_Real_gfx6_gfx7_gfx10<bits<8> op> :
Expand Down Expand Up @@ -2205,7 +2205,7 @@ defm S_ABS_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x034>;
multiclass SOP2_Real_gfx12<bits<7> op, string name = !tolower(NAME)> {
defvar ps = !cast<SOP2_Pseudo>(NAME);
def _gfx12 : SOP2_Real32<op, ps, name>,
Select_gfx12<ps.Mnemonic>;
Select_gfx12<ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>;
}
Expand All @@ -2222,7 +2222,7 @@ defm S_MAXIMUM_F16 : SOP2_Real_gfx12<0x052>;
multiclass SOP2_Real_gfx11<bits<7> op, string name = !tolower(NAME)> {
defvar ps = !cast<SOP2_Pseudo>(NAME);
def _gfx11 : SOP2_Real32<op, ps, name>,
Select_gfx11<ps.Mnemonic>;
Select_gfx11<ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX11Only]>;
}
Expand Down Expand Up @@ -2283,12 +2283,12 @@ defm S_MUL_U64 : SOP2_Real_gfx12<0x055>;

multiclass SOP2_Real_FMAK_gfx12<bits<7> op> {
def _gfx12 : SOP2_Real64<op, !cast<SOP2_Pseudo>(NAME)>,
Select_gfx12<!cast<SOP2_Pseudo>(NAME).Mnemonic>;
Select_gfx12<!cast<SOP2_Pseudo>(NAME).PseudoInstr>;
}

multiclass SOP2_Real_FMAK_gfx11<bits<7> op> {
def _gfx11 : SOP2_Real64<op, !cast<SOP2_Pseudo>(NAME)>,
Select_gfx11<!cast<SOP2_Pseudo>(NAME).Mnemonic>;
Select_gfx11<!cast<SOP2_Pseudo>(NAME).PseudoInstr>;
}

multiclass SOP2_Real_FMAK_gfx11_gfx12<bits<7> op> :
Expand Down Expand Up @@ -2325,7 +2325,7 @@ defm S_MAX_F16 : SOP2_Real_gfx11_Renamed_gfx12<0x04c, "s_max_num_f16">;
multiclass SOP2_Real_gfx10<bits<7> op> {
defvar ps = !cast<SOP2_Pseudo>(NAME);
def _gfx10 : SOP2_Real32<op, ps>,
Select_gfx10<ps.Mnemonic>;
Select_gfx10<ps.PseudoInstr>;
}

multiclass SOP2_Real_gfx10_gfx11_gfx12<bits<7> op> :
Expand All @@ -2348,7 +2348,7 @@ defm S_MUL_HI_I32 : SOP2_Real_gfx10<0x036>;
multiclass SOP2_Real_gfx6_gfx7<bits<7> op> {
defvar ps = !cast<SOP2_Pseudo>(NAME);
def _gfx6_gfx7 : SOP2_Real32<op, ps>,
Select_gfx6_gfx7<ps.Mnemonic>;
Select_gfx6_gfx7<ps.PseudoInstr>;
}

multiclass SOP2_Real_gfx6_gfx7_gfx10<bits<7> op> :
Expand Down Expand Up @@ -2410,24 +2410,24 @@ defm S_ABSDIFF_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x02c>;
multiclass SOPK_Real32_gfx12<bits<5> op, string name = !tolower(NAME)> {
defvar ps = !cast<SOPK_Pseudo>(NAME);
def _gfx12 : SOPK_Real32<op, ps, name>,
Select_gfx12<ps.Mnemonic>;
Select_gfx12<ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>;
}

multiclass SOPK_Real32_gfx11<bits<5> op> {
def _gfx11 : SOPK_Real32<op, !cast<SOPK_Pseudo>(NAME)>,
Select_gfx11<!cast<SOPK_Pseudo>(NAME).Mnemonic>;
Select_gfx11<!cast<SOPK_Pseudo>(NAME).PseudoInstr>;
}

multiclass SOPK_Real64_gfx12<bits<5> op> {
def _gfx12 : SOPK_Real64<op, !cast<SOPK_Pseudo>(NAME)>,
Select_gfx12<!cast<SOPK_Pseudo>(NAME).Mnemonic>;
Select_gfx12<!cast<SOPK_Pseudo>(NAME).PseudoInstr>;
}

multiclass SOPK_Real64_gfx11<bits<5> op> {
def _gfx11 : SOPK_Real64<op, !cast<SOPK_Pseudo>(NAME)>,
Select_gfx11<!cast<SOPK_Pseudo>(NAME).Mnemonic>;
Select_gfx11<!cast<SOPK_Pseudo>(NAME).PseudoInstr>;
}

multiclass SOPK_Real32_gfx11_gfx12<bits<5> op> :
Expand All @@ -2454,13 +2454,13 @@ defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx11<0x01b>;
multiclass SOPK_Real32_gfx10<bits<5> op> {
defvar ps = !cast<SOPK_Pseudo>(NAME);
def _gfx10 : SOPK_Real32<op, ps>,
Select_gfx10<ps.Mnemonic>;
Select_gfx10<ps.PseudoInstr>;
}

multiclass SOPK_Real64_gfx10<bits<5> op> {
defvar ps = !cast<SOPK_Pseudo>(NAME);
def _gfx10 : SOPK_Real64<op, ps>,
Select_gfx10<ps.Mnemonic>;
Select_gfx10<ps.PseudoInstr>;
}

multiclass SOPK_Real32_gfx10_gfx11<bits<5> op> :
Expand All @@ -2485,13 +2485,13 @@ defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx10<0x01c>;
multiclass SOPK_Real32_gfx6_gfx7<bits<5> op> {
defvar ps = !cast<SOPK_Pseudo>(NAME);
def _gfx6_gfx7 : SOPK_Real32<op, ps>,
Select_gfx6_gfx7<ps.Mnemonic>;
Select_gfx6_gfx7<ps.PseudoInstr>;
}

multiclass SOPK_Real64_gfx6_gfx7<bits<5> op> {
defvar ps = !cast<SOPK_Pseudo>(NAME);
def _gfx6_gfx7 : SOPK_Real64<op, ps>,
Select_gfx6_gfx7<ps.Mnemonic>;
Select_gfx6_gfx7<ps.PseudoInstr>;
}

multiclass SOPK_Real32_gfx6_gfx7_gfx10<bits<5> op> :
Expand Down Expand Up @@ -2539,7 +2539,7 @@ defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx6_gfx7_gfx10<0x015>;
multiclass SOPP_Real_32_gfx12<bits<7> op, string name = !tolower(NAME)> {
defvar ps = !cast<SOPP_Pseudo>(NAME);
def _gfx12 : SOPP_Real_32<op, ps, name>,
Select_gfx12<ps.Mnemonic>;
Select_gfx12<ps.PseudoInstr>;
if !ne(ps.Mnemonic, name) then
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>;
}
Expand All @@ -2564,21 +2564,21 @@ defm S_WAIT_STORECNT_DSCNT : SOPP_Real_32_gfx12<0x049>;
multiclass SOPP_Real_32_gfx11<bits<7> op, string name = !tolower(NAME)> {
defvar ps = !cast<SOPP_Pseudo>(NAME);
def _gfx11 : SOPP_Real_32<op, ps, name>,
Select_gfx11<ps.Mnemonic>,
Select_gfx11<ps.PseudoInstr>,
SOPPRelaxTable<0, ps.KeyName, "_gfx11">;
if !ne(ps.Mnemonic, name) then
def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX11Only]>;
}

multiclass SOPP_Real_64_gfx12<bits<7> op> {
def _gfx12 : SOPP_Real_64<op, !cast<SOPP_Pseudo>(NAME), !cast<SOPP_Pseudo>(NAME).Mnemonic>,
Select_gfx12<!cast<SOPP_Pseudo>(NAME).Mnemonic>,
Select_gfx12<!cast<SOPP_Pseudo>(NAME).PseudoInstr>,
SOPPRelaxTable<1, !cast<SOPP_Pseudo>(NAME).KeyName, "_gfx12">;
}

multiclass SOPP_Real_64_gfx11<bits<7> op> {
def _gfx11 : SOPP_Real_64<op, !cast<SOPP_Pseudo>(NAME), !cast<SOPP_Pseudo>(NAME).Mnemonic>,
Select_gfx11<!cast<SOPP_Pseudo>(NAME).Mnemonic>,
Select_gfx11<!cast<SOPP_Pseudo>(NAME).PseudoInstr>,
SOPPRelaxTable<1, !cast<SOPP_Pseudo>(NAME).KeyName, "_gfx11">;
}

Expand Down Expand Up @@ -2654,21 +2654,21 @@ defm S_SINGLEUSE_VDST : SOPP_Real_32_gfx11_gfx12<0x013>;
multiclass SOPP_Real_32_gfx6_gfx7<bits<7> op> {
defvar ps = !cast<SOPP_Pseudo>(NAME);
def _gfx6_gfx7 : SOPP_Real_32<op, ps, !cast<SOPP_Pseudo>(NAME).Mnemonic>,
Select_gfx6_gfx7<ps.Mnemonic>,
Select_gfx6_gfx7<ps.PseudoInstr>,
SOPPRelaxTable<0, ps.KeyName, "_gfx6_gfx7">;
}

multiclass SOPP_Real_32_gfx8_gfx9<bits<7> op> {
defvar ps = !cast<SOPP_Pseudo>(NAME);
def _vi : SOPP_Real_32<op, ps>,
Select_vi<ps.Mnemonic>,
Select_vi<ps.PseudoInstr>,
SOPPRelaxTable<0, ps.KeyName, "_vi">;
}

multiclass SOPP_Real_32_gfx10<bits<7> op> {
defvar ps = !cast<SOPP_Pseudo>(NAME);
def _gfx10 : SOPP_Real_32<op, ps>,
Select_gfx10<ps.Mnemonic>,
Select_gfx10<ps.PseudoInstr>,
SOPPRelaxTable<0, ps.KeyName, "_gfx10">;
}

Expand All @@ -2691,21 +2691,21 @@ multiclass SOPP_Real_32_gfx10_gfx11_gfx12<bits<7> op> :
multiclass SOPP_Real_64_gfx6_gfx7<bits<7> op> {
defvar ps = !cast<SOPP_Pseudo>(NAME);
def _gfx6_gfx7 : SOPP_Real_64<op, ps>,
Select_gfx6_gfx7<ps.Mnemonic>,
Select_gfx6_gfx7<ps.PseudoInstr>,
SOPPRelaxTable<1, ps.KeyName, "_gfx6_gfx7">;
}

multiclass SOPP_Real_64_gfx8_gfx9<bits<7> op> {
defvar ps = !cast<SOPP_Pseudo>(NAME);
def _vi : SOPP_Real_64<op, ps>,
Select_vi<ps.Mnemonic>,
Select_vi<ps.PseudoInstr>,
SOPPRelaxTable<1, ps.KeyName, "_vi">;
}

multiclass SOPP_Real_64_gfx10<bits<7> op> {
defvar ps = !cast<SOPP_Pseudo>(NAME);
def _gfx10 : SOPP_Real_64<op, ps>,
Select_gfx10<ps.Mnemonic>,
Select_gfx10<ps.PseudoInstr>,
SOPPRelaxTable<1, ps.KeyName, "_gfx10">;
}

Expand Down Expand Up @@ -2771,12 +2771,12 @@ defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_

multiclass SOPC_Real_gfx12<bits<7> op> {
def _gfx12 : SOPC_Real<op, !cast<SOPC_Pseudo>(NAME)>,
Select_gfx12<!cast<SOPC_Pseudo>(NAME).Mnemonic>;
Select_gfx12<!cast<SOPC_Pseudo>(NAME).PseudoInstr>;
}

multiclass SOPC_Real_gfx11<bits<7> op> {
def _gfx11 : SOPC_Real<op, !cast<SOPC_Pseudo>(NAME)>,
Select_gfx11<!cast<SOPC_Pseudo>(NAME).Mnemonic>;
Select_gfx11<!cast<SOPC_Pseudo>(NAME).PseudoInstr>;
}

multiclass SOPC_Real_gfx11_gfx12<bits<7> op> :
Expand Down Expand Up @@ -2826,19 +2826,19 @@ defm S_CMP_NLT_F16 : SOPC_Real_gfx11_gfx12<0x5e>;
multiclass SOPC_Real_gfx6_gfx7<bits<7> op> {
defvar ps = !cast<SOPC_Pseudo>(NAME);
def _gfx6_gfx7 : SOPC_Real<op, ps>,
Select_gfx6_gfx7<ps.Mnemonic>;
Select_gfx6_gfx7<ps.PseudoInstr>;
}

multiclass SOPC_Real_gfx8_gfx9<bits<7> op> {
defvar ps = !cast<SOPC_Pseudo>(NAME);
def _vi : SOPC_Real<op, ps>,
Select_vi<ps.Mnemonic>;
Select_vi<ps.PseudoInstr>;
}

multiclass SOPC_Real_gfx10<bits<7> op> {
defvar ps = !cast<SOPC_Pseudo>(NAME);
def _gfx10 : SOPC_Real<op, ps>,
Select_gfx10<ps.Mnemonic>;
Select_gfx10<ps.PseudoInstr>;
}

multiclass SOPC_Real_gfx8_gfx9_gfx10<bits<7> op> :
Expand Down Expand Up @@ -2878,15 +2878,15 @@ defm S_CMP_LG_U64 : SOPC_Real_gfx8_gfx9_gfx10<0x13>;

class SOP1_Real_vi<bits<8> op, SOP1_Pseudo ps> :
SOP1_Real<op, ps>,
Select_vi<ps.Mnemonic>;
Select_vi<ps.PseudoInstr>;

class SOP2_Real_vi<bits<7> op, SOP2_Pseudo ps> :
SOP2_Real32<op, ps>,
Select_vi<ps.Mnemonic>;
Select_vi<ps.PseudoInstr>;

class SOPK_Real_vi<bits<5> op, SOPK_Pseudo ps> :
SOPK_Real32<op, ps>,
Select_vi<ps.Mnemonic>;
Select_vi<ps.PseudoInstr>;

def S_MOV_B32_vi : SOP1_Real_vi <0x00, S_MOV_B32>;
def S_MOV_B64_vi : SOP1_Real_vi <0x01, S_MOV_B64>;
Expand Down Expand Up @@ -3007,7 +3007,7 @@ def S_GETREG_B32_vi : SOPK_Real_vi <0x11, S_GETREG_B32>;
def S_SETREG_B32_vi : SOPK_Real_vi <0x12, S_SETREG_B32>;
//def S_GETREG_REGRD_B32_vi : SOPK_Real_vi <0x13, S_GETREG_REGRD_B32>; // see pseudo for comments
def S_SETREG_IMM32_B32_vi : SOPK_Real64<0x14, S_SETREG_IMM32_B32>,
Select_vi<S_SETREG_IMM32_B32.Mnemonic>;
Select_vi<S_SETREG_IMM32_B32.PseudoInstr>;

def S_CALL_B64_vi : SOPK_Real_vi <0x15, S_CALL_B64>;

Expand Down