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[AArch64] Remove copy in SVE/SME predicate spill and fill #81716

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Merged
merged 19 commits into from
Apr 9, 2024
Merged

[AArch64] Remove copy in SVE/SME predicate spill and fill #81716

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c0c0609
[AArch64] Remove copy in SVE/SME predicate spill
SamTebbs33 Feb 13, 2024
929b111
fixup: constrain reg class instead of convert
SamTebbs33 Feb 21, 2024
514b9b5
fixup: let predicate spill and fill take ppr or pnr
SamTebbs33 Feb 27, 2024
264a844
fixup: remove braces
SamTebbs33 Feb 27, 2024
53a3177
fixup: add decode function
SamTebbs33 Feb 28, 2024
6a4502c
fixup: remove inst aliases
SamTebbs33 Feb 28, 2024
808ddbb
fixup: match reg class in AArch64AsmParser
SamTebbs33 Feb 28, 2024
ed8519e
Add svcount to reg class
SamTebbs33 Feb 28, 2024
6a55451
fixup: format definitions
SamTebbs33 Feb 28, 2024
a229c76
fixup: use reg class numbers in MIR tests
SamTebbs33 Feb 29, 2024
8c5b567
fixup: Add parsing and rendering functions
SamTebbs33 Mar 6, 2024
a64ca22
fixup: remove spaces
SamTebbs33 Mar 7, 2024
9e59c45
fixup: format decode function
SamTebbs33 Mar 7, 2024
1a398e1
fixup: merge pprorpnr and ppraspnr handling
SamTebbs33 Mar 20, 2024
2f6d418
fixup: combine ppr and pnr stack slot handling
SamTebbs33 Apr 2, 2024
f06c0ce
fixup: add <= pn15 to asm parser
SamTebbs33 Apr 2, 2024
23b051b
fixup: simplify load/storeRegToStackSlot
SamTebbs33 Apr 5, 2024
a53aeb4
fixup: remove extra parentheses
SamTebbs33 Apr 5, 2024
03aabd2
fixup: remove IsPPR and move error match case statement
SamTebbs33 Apr 9, 2024
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37 changes: 12 additions & 25 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4810,29 +4810,20 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
Opc = AArch64::STRBui;
break;
case 2:
case 2: {
bool IsPNR = AArch64::PNRRegClass.hasSubClassEq(RC);
if (AArch64::FPR16RegClass.hasSubClassEq(RC))
Opc = AArch64::STRHui;
else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
else if (IsPNR || AArch64::PPRRegClass.hasSubClassEq(RC)) {
assert(Subtarget.hasSVEorSME() &&
"Unexpected register store without SVE store instructions");
Opc = AArch64::STR_PXI;
StackID = TargetStackID::ScalableVector;
} else if (AArch64::PNRRegClass.hasSubClassEq(RC)) {
assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
assert((!IsPNR || Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
"Unexpected register store without SVE2p1 or SME2");
if (SrcReg.isVirtual()) {
auto NewSrcReg =
MF.getRegInfo().createVirtualRegister(&AArch64::PPRRegClass);
BuildMI(MBB, MBBI, DebugLoc(), get(TargetOpcode::COPY), NewSrcReg)
.addReg(SrcReg);
SrcReg = NewSrcReg;
} else
SrcReg = (SrcReg - AArch64::PN0) + AArch64::P0;
Opc = AArch64::STR_PXI;
StackID = TargetStackID::ScalableVector;
}
break;
}
case 4:
if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
Opc = AArch64::STRWui;
Expand Down Expand Up @@ -4993,26 +4984,22 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
Opc = AArch64::LDRBui;
break;
case 2:
case 2: {
bool IsPNR = AArch64::PNRRegClass.hasSubClassEq(RC);
if (AArch64::FPR16RegClass.hasSubClassEq(RC))
Opc = AArch64::LDRHui;
else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
else if (IsPNR || AArch64::PPRRegClass.hasSubClassEq(RC)) {
assert(Subtarget.hasSVEorSME() &&
"Unexpected register load without SVE load instructions");
Opc = AArch64::LDR_PXI;
StackID = TargetStackID::ScalableVector;
} else if (AArch64::PNRRegClass.hasSubClassEq(RC)) {
assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
assert((!IsPNR || Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
"Unexpected register load without SVE2p1 or SME2");
PNRReg = DestReg;
if (DestReg.isVirtual())
DestReg = MF.getRegInfo().createVirtualRegister(&AArch64::PPRRegClass);
else
DestReg = (DestReg - AArch64::PN0) + AArch64::P0;
if (IsPNR)
PNRReg = DestReg;
Opc = AArch64::LDR_PXI;
StackID = TargetStackID::ScalableVector;
}
break;
}
case 4:
if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
Opc = AArch64::LDRWui;
Expand Down
34 changes: 23 additions & 11 deletions llvm/lib/Target/AArch64/AArch64RegisterInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -953,17 +953,6 @@ class PNRAsmOperand<string name, string RegClass, int Width>: AsmOperandClass {
let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>";
}

let RenderMethod = "addPNRasPPRRegOperands" in {
def PNRasPPROpAny : PNRAsmOperand<"PNRasPPRPredicateAny", "PNR", 0>;
def PNRasPPROp8 : PNRAsmOperand<"PNRasPPRPredicateB", "PNR", 8>;
}

class PNRasPPRRegOp<string Suffix, AsmOperandClass C, ElementSizeEnum Size,
RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}

def PNRasPPRAny : PNRasPPRRegOp<"", PNRasPPROpAny, ElementSizeNone, PPR>;
def PNRasPPR8 : PNRasPPRRegOp<"b", PNRasPPROp8, ElementSizeB, PPR>;

def PNRAsmOpAny: PNRAsmOperand<"PNPredicateAny", "PNR", 0>;
def PNRAsmOp8 : PNRAsmOperand<"PNPredicateB", "PNR", 8>;
def PNRAsmOp16 : PNRAsmOperand<"PNPredicateH", "PNR", 16>;
Expand Down Expand Up @@ -1004,6 +993,29 @@ let Namespace = "AArch64" in {
def psub1 : SubRegIndex<16, -1>;
}

class PPRorPNRClass : RegisterClass<
"AArch64",
[ nxv16i1, nxv8i1, nxv4i1, nxv2i1, nxv1i1, aarch64svcount ], 16,
(add PPR, PNR)> {
let Size = 16;
}

class PPRorPNRAsmOperand<string name, string RegClass, int Width>: AsmOperandClass {
let Name = "SVE" # name # "Reg";
let PredicateMethod = "isSVEPredicateOrPredicateAsCounterRegOfWidth<"
# Width # ", " # "AArch64::"
# RegClass # "RegClassID>";
let DiagnosticType = "InvalidSVE" # name # "Reg";
let RenderMethod = "addPPRorPNRRegOperands";
let ParserMethod = "tryParseSVEPredicateOrPredicateAsCounterVector";
}

def PPRorPNR : PPRorPNRClass;
def PPRorPNRAsmOp8 : PPRorPNRAsmOperand<"PPRorPNRB", "PPRorPNR", 8>;
def PPRorPNRAsmOpAny : PPRorPNRAsmOperand<"PPRorPNRAny", "PPRorPNR", 0>;
def PPRorPNRAny : PPRRegOp<"", PPRorPNRAsmOpAny, ElementSizeNone, PPRorPNR>;
def PPRorPNR8 : PPRRegOp<"b", PPRorPNRAsmOp8, ElementSizeB, PPRorPNR>;

// Pairs of SVE predicate vector registers.
def PSeqPairs : RegisterTuples<[psub0, psub1], [(rotl PPR, 0), (rotl PPR, 1)]>;

Expand Down
14 changes: 2 additions & 12 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -4017,20 +4017,10 @@ let Predicates = [HasSVEorSME] in {

// Aliases for existing SVE instructions for which predicate-as-counter are
// accepted as an operand to the instruction
def : InstAlias<"ldr $Pt, [$Rn, $imm9, mul vl]",
(LDR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
def : InstAlias<"ldr $Pt, [$Rn]",
(LDR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, 0), 0>;

def : InstAlias<"str $Pt, [$Rn, $imm9, mul vl]",
(STR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
def : InstAlias<"str $Pt, [$Rn]",
(STR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, 0), 0>;

def : InstAlias<"mov $Pd, $Pn",
(ORR_PPzPP PNRasPPR8:$Pd, PNRasPPR8:$Pn, PNRasPPR8:$Pn, PNRasPPR8:$Pn), 0>;
(ORR_PPzPP PPRorPNR8:$Pd, PPRorPNR8:$Pn, PPRorPNR8:$Pn, PPRorPNR8:$Pn), 0>;

def : InstAlias<"pfalse\t$Pd", (PFALSE PNRasPPR8:$Pd), 0>;
def : InstAlias<"pfalse\t$Pd", (PFALSE PPRorPNR8:$Pd), 0>;

}

Expand Down
44 changes: 40 additions & 4 deletions llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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Expand Up @@ -276,6 +276,8 @@ class AArch64AsmParser : public MCTargetAsmParser {
ParseStatus tryParseSVEDataVector(OperandVector &Operands);
template <RegKind RK>
ParseStatus tryParseSVEPredicateVector(OperandVector &Operands);
ParseStatus
tryParseSVEPredicateOrPredicateAsCounterVector(OperandVector &Operands);
template <RegKind VectorKind>
ParseStatus tryParseVectorList(OperandVector &Operands,
bool ExpectMatch = false);
Expand Down Expand Up @@ -1241,6 +1243,7 @@ class AArch64Operand : public MCParsedAsmOperand {
case AArch64::PPR_p8to15RegClassID:
case AArch64::PNRRegClassID:
case AArch64::PNR_p8to15RegClassID:
case AArch64::PPRorPNRRegClassID:
RK = RegKind::SVEPredicateAsCounter;
break;
default:
Expand All @@ -1264,6 +1267,7 @@ class AArch64Operand : public MCParsedAsmOperand {
case AArch64::PPR_p8to15RegClassID:
case AArch64::PNRRegClassID:
case AArch64::PNR_p8to15RegClassID:
case AArch64::PPRorPNRRegClassID:
RK = RegKind::SVEPredicateVector;
break;
default:
Expand All @@ -1290,6 +1294,20 @@ class AArch64Operand : public MCParsedAsmOperand {
return DiagnosticPredicateTy::NearMatch;
}

template <int ElementWidth, unsigned Class>
DiagnosticPredicate isSVEPredicateOrPredicateAsCounterRegOfWidth() const {
if (Kind != k_Register || (Reg.Kind != RegKind::SVEPredicateAsCounter &&
Reg.Kind != RegKind::SVEPredicateVector))
return DiagnosticPredicateTy::NoMatch;

if ((isSVEPredicateAsCounterReg<Class>() ||
isSVEPredicateVectorRegOfWidth<ElementWidth, Class>()) &&
Reg.ElementWidth == ElementWidth)
return DiagnosticPredicateTy::Match;

return DiagnosticPredicateTy::NearMatch;
}

template <int ElementWidth, unsigned Class>
DiagnosticPredicate isSVEPredicateAsCounterRegOfWidth() const {
if (Kind != k_Register || Reg.Kind != RegKind::SVEPredicateAsCounter)
Expand Down Expand Up @@ -1770,6 +1788,15 @@ class AArch64Operand : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::createReg(AArch64::Z0 + getReg() - Base));
}

void addPPRorPNRRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
unsigned Reg = getReg();
// Normalise to PPR
if (Reg >= AArch64::PN0 && Reg <= AArch64::PN15)
Reg = Reg - AArch64::PN0 + AArch64::P0;
Inst.addOperand(MCOperand::createReg(Reg));
}

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Can addPNRasPPRRegOperands be removed now? Or perhaps I should ask: is PNRasPPR still required, or can those instructions that use it also use PPRorPNRRegOperand ?

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PPRasPNR can be removed. Thanks for the idea.

void addPNRasPPRRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(
Expand Down Expand Up @@ -4167,6 +4194,15 @@ ParseStatus AArch64AsmParser::tryParseVectorRegister(MCRegister &Reg,
return ParseStatus::NoMatch;
}

ParseStatus AArch64AsmParser::tryParseSVEPredicateOrPredicateAsCounterVector(
OperandVector &Operands) {
ParseStatus Status =
tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>(Operands);
if (!Status.isSuccess())
Status = tryParseSVEPredicateVector<RegKind::SVEPredicateVector>(Operands);
return Status;
}

/// tryParseSVEPredicateVector - Parse a SVE predicate register operand.
template <RegKind RK>
ParseStatus
Expand Down Expand Up @@ -6019,6 +6055,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
return Error(Loc, "Invalid restricted vector register, expected z0.d..z15.d");
case Match_InvalidSVEPattern:
return Error(Loc, "invalid predicate pattern");
case Match_InvalidSVEPPRorPNRAnyReg:
case Match_InvalidSVEPPRorPNRBReg:
case Match_InvalidSVEPredicateAnyReg:
case Match_InvalidSVEPredicateBReg:
case Match_InvalidSVEPredicateHReg:
Expand Down Expand Up @@ -6131,9 +6169,6 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
case Match_AddSubLSLImm3ShiftLarge:
return Error(Loc,
"expected 'lsl' with optional integer in range [0, 7]");
case Match_InvalidSVEPNRasPPRPredicateBReg:
return Error(Loc,
"Expected predicate-as-counter register name with .B suffix");
default:
llvm_unreachable("unexpected error code!");
}
Expand Down Expand Up @@ -6653,6 +6688,8 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidZPR_4b16:
case Match_InvalidZPR_4b32:
case Match_InvalidZPR_4b64:
case Match_InvalidSVEPPRorPNRAnyReg:
case Match_InvalidSVEPPRorPNRBReg:
case Match_InvalidSVEPredicateAnyReg:
case Match_InvalidSVEPattern:
case Match_InvalidSVEVecLenSpecifier:
Expand Down Expand Up @@ -6714,7 +6751,6 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidSVEVectorListStrided4x16:
case Match_InvalidSVEVectorListStrided4x32:
case Match_InvalidSVEVectorListStrided4x64:
case Match_InvalidSVEPNRasPPRPredicateBReg:
case Match_MSR:
case Match_MRS: {
if (ErrorInfo >= Operands.size())
Expand Down
15 changes: 15 additions & 0 deletions llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
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Expand Up @@ -143,6 +143,9 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder);
static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr,
const MCDisassembler *Decoder);
static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder);
Expand Down Expand Up @@ -741,6 +744,18 @@ static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
return Success;
}

static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo,
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Cleanup suggestion for a separate patch:

All these decoder classes looks rather identical, it would be nice to clean this up with something like this:

template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>
static DecodeStatus DecodeSimpleReg(MCInst &Inst, unsigned RegNo,
                                                uint64_t Addr,
                                                const MCDisassembler *Decoder) {
  if (RegNo > (NumRegsInClass-1))
    return Fail;

  unsigned Register =
      AArch64MCRegisterClasses[RegClassID].getRegister(RegNo);
  Inst.addOperand(MCOperand::createReg(Register + FirstReg));
  return Success;
}

And then remove the other functions and just specify e.g. DecodeSimpleReg<AArch64::PPRorPNRRegClassID, 0, 16> in the .td file.

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That sounds good to me. We can do it in a separate patch.

uint64_t Addr,
const MCDisassembler *Decoder) {
if (RegNo > 15)
return Fail;

unsigned Register =
AArch64MCRegisterClasses[AArch64::PPRorPNRRegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register));
return Success;
}

static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr,
const MCDisassembler *Decoder) {
Expand Down
15 changes: 1 addition & 14 deletions llvm/lib/Target/AArch64/SMEInstrFormats.td
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Expand Up @@ -1303,7 +1303,7 @@ multiclass sve2_clamp<string asm, bit U, SDPatternOperator op> {
}

class sve2_int_perm_sel_p<string asm, PPRRegOp ppr_ty, Operand imm_ty>
: I<(outs PPRAny:$Pd), (ins PPRAny:$Pn, ppr_ty:$Pm,
: I<(outs PPRorPNRAny:$Pd), (ins PPRorPNRAny:$Pn, ppr_ty:$Pm,
MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm),
asm, "\t$Pd, $Pn, $Pm[$Rv, $imm]", "", []>,
Sched<[]> {
Expand Down Expand Up @@ -1347,19 +1347,6 @@ multiclass sve2_int_perm_sel_p<string asm, SDPatternOperator op> {
let Inst{20-18} = 0b000;
}

def : InstAlias<asm # "\t$Pd, $Pn, $Pm[$Rv, $imm]",
(!cast<Instruction>(NAME # _B) PNRasPPRAny:$Pd,
PNRasPPRAny:$Pn, PPR8:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm), 0>;
def : InstAlias<asm # "\t$Pd, $Pn, $Pm[$Rv, $imm]",
(!cast<Instruction>(NAME # _H) PNRasPPRAny:$Pd,
PNRasPPRAny:$Pn, PPR16:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm), 0>;
def : InstAlias<asm # "\t$Pd, $Pn, $Pm[$Rv, $imm]",
(!cast<Instruction>(NAME # _S) PNRasPPRAny:$Pd,
PNRasPPRAny:$Pn, PPR32:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm), 0>;
def : InstAlias<asm # "\t$Pd, $Pn, $Pm[$Rv, $imm]",
(!cast<Instruction>(NAME # _D) PNRasPPRAny:$Pd,
PNRasPPRAny:$Pn, PPR64:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm), 0>;

def : Pat<(nxv16i1 (op (nxv16i1 PPRAny:$Pn), (nxv16i1 PPR8:$Pm),
MatrixIndexGPR32Op12_15:$idx)),
(!cast<Instruction>(NAME # _B) $Pn, $Pm, $idx, 0)>;
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/AArch64/SVEInstrFormats.td
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Expand Up @@ -740,7 +740,7 @@ let hasNoSchedulingInfo = 1 in {
//===----------------------------------------------------------------------===//

class sve_int_pfalse<bits<6> opc, string asm>
: I<(outs PPR8:$Pd), (ins),
: I<(outs PPRorPNR8:$Pd), (ins),
asm, "\t$Pd",
"",
[]>, Sched<[]> {
Expand Down Expand Up @@ -1848,7 +1848,7 @@ multiclass sve_int_sel_vvv<string asm, SDPatternOperator op> {
//===----------------------------------------------------------------------===//

class sve_int_pred_log<bits<4> opc, string asm>
: I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm),
: I<(outs PPRorPNR8:$Pd), (ins PPRorPNRAny:$Pg, PPRorPNR8:$Pn, PPRorPNR8:$Pm),
asm, "\t$Pd, $Pg/z, $Pn, $Pm",
"",
[]>, Sched<[]> {
Expand Down Expand Up @@ -6689,7 +6689,7 @@ multiclass sve_mem_z_spill<string asm> {
}

class sve_mem_p_spill<string asm>
: I<(outs), (ins PPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9),
: I<(outs), (ins PPRorPNRAny:$Pt, GPR64sp:$Rn, simm9:$imm9),
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This removes the need for having the following InstAliases in AArch64SVEInstrInfo.td:

// Aliases for existing SVE instructions for which predicate-as-counter are
// accepted as an operand to the instruction
def : InstAlias<"ldr $Pt, [$Rn, $imm9, mul vl]",
               (LDR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
def : InstAlias<"ldr $Pt, [$Rn]",
               (LDR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, 0), 0>;

def : InstAlias<"str $Pt, [$Rn, $imm9, mul vl]",
               (STR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
def : InstAlias<"str $Pt, [$Rn]",
               (STR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, 0), 0>;

Can you remove them?

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Done.

asm, "\t$Pt, [$Rn, $imm9, mul vl]",
"",
[]>, Sched<[]> {
Expand All @@ -6712,7 +6712,7 @@ multiclass sve_mem_p_spill<string asm> {
def NAME : sve_mem_p_spill<asm>;

def : InstAlias<asm # "\t$Pt, [$Rn]",
(!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
(!cast<Instruction>(NAME) PPRorPNRAny:$Pt, GPR64sp:$Rn, 0), 1>;
}

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -7858,7 +7858,7 @@ multiclass sve_mem_z_fill<string asm> {
}

class sve_mem_p_fill<string asm>
: I<(outs PPRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9),
: I<(outs PPRorPNRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9),
asm, "\t$Pt, [$Rn, $imm9, mul vl]",
"",
[]>, Sched<[]> {
Expand All @@ -7881,7 +7881,7 @@ multiclass sve_mem_p_fill<string asm> {
def NAME : sve_mem_p_fill<asm>;

def : InstAlias<asm # "\t$Pt, [$Rn]",
(!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
(!cast<Instruction>(NAME) PPRorPNRAny:$Pt, GPR64sp:$Rn, 0), 1>;
}

class sve2_mem_gldnt_vs_base<bits<5> opc, dag iops, string asm,
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
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Expand Up @@ -57,11 +57,11 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: inlineasm_virt_reg_output
; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1310730 /* regdef:PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15 */, def %0
; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1310730 /* regdef:GPR32common */, def %0:gpr32common
INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0:gpr32common
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Suggested change
INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0:gpr32common
INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, {{[0-9]+}} /* regdef:GPR32common */, def %0:gpr32common

(same in other places)

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We can only use the regex in a CHECK statement, not in the IR being tested.

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Ah I didn't spot the leading ;!

In that case, I would suggest not using a regex for these numbers, because they must match the ones from the MIR.

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Good point, I've changed the .mir tests to explicitly match the regclass numbers.

%1:_(s32) = COPY %0
$w0 = COPY %1(s32)
RET_ReallyLR implicit $w0
Expand All @@ -75,12 +75,12 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: inlineasm_virt_mixed_types
; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1310730 /* regdef:PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15 */, def %0, 2162698 /* regdef:WSeqPairsClass */, def %1
; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0, {{[0-9]+}} /* regdef:FPR64 */, def %1
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY %1
; CHECK-NEXT: $d0 = COPY [[COPY1]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1310730 /* regdef:GPR32common */, def %0:gpr32common, 2162698 /* regdef:FPR64 */, def %1:fpr64
INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0:gpr32common, 2621450 /* regdef:FPR64 */, def %1:fpr64
%3:_(s32) = COPY %0
%4:_(s64) = COPY %1
$d0 = COPY %4(s64)
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