Skip to content

[RISCV] Register fixed stack slots for callee saved registers for -ms… #81392

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Feb 13, 2024
Merged

[RISCV] Register fixed stack slots for callee saved registers for -ms… #81392

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
55c550d
[RISCV] Register fixed stack slots for callee saved registers for -ms…
topperc Feb 10, 2024
ffa6d74
fixup! Use MCPhysReg and int8_t to shrink FixedCSRFIMap.
topperc Feb 13, 2024
7736254
fixup! Calculate the correct callee saved size for RVV.
topperc Feb 13, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
163 changes: 99 additions & 64 deletions llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -291,9 +291,7 @@ static Register getMaxPushPopReg(const MachineFunction &MF,
const std::vector<CalleeSavedInfo> &CSI) {
Register MaxPushPopReg = RISCV::NoRegister;
for (auto &CS : CSI) {
// RISCVRegisterInfo::hasReservedSpillSlot assigns negative frame indices to
// registers which can be saved by Zcmp Push.
if (CS.getFrameIdx() < 0)
if (llvm::is_contained(AllPopRegs, CS.getReg().id()))
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Should we merge AllPopRegs and FixedCSRFIMap?

MaxPushPopReg = std::max(MaxPushPopReg.id(), CS.getReg().id());
}
// if rlist is {rs, s0-s10}, then s11 will also be included
Expand Down Expand Up @@ -532,8 +530,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,

// FIXME (note copied from Lanai): This appears to be overallocating. Needs
// investigation. Get the number of bytes to allocate from the FrameInfo.
uint64_t StackSize = getStackSizeWithRVVPadding(MF);
uint64_t RealStackSize = StackSize + RVFI->getReservedSpillsSize();
uint64_t RealStackSize = getStackSizeWithRVVPadding(MF);
uint64_t StackSize = RealStackSize - RVFI->getReservedSpillsSize();
uint64_t RVVStackSize = RVFI->getRVVStackSize();

// Early exit if there is no need to allocate on the stack
Expand Down Expand Up @@ -590,20 +588,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
// directives.
for (const auto &Entry : CSI) {
int FrameIdx = Entry.getFrameIdx();
int64_t Offset;
// Offsets for objects with fixed locations (IE: those saved by libcall) are
// simply calculated from the frame index.
if (FrameIdx < 0) {
if (RVFI->isPushable(MF)) {
// Callee-saved register stored by Zcmp push is in reverse order.
Offset = -(FrameIdx + RVFI->getRVPushRegs() + 1) *
(int64_t)STI.getXLen() / 8;
} else {
Offset = FrameIdx * (int64_t)STI.getXLen() / 8;
}
} else {
Offset = MFI.getObjectOffset(FrameIdx) - RVFI->getReservedSpillsSize();
}
int64_t Offset = MFI.getObjectOffset(FrameIdx);
Register Reg = Entry.getReg();
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, RI->getDwarfRegNum(Reg, true), Offset));
Expand Down Expand Up @@ -746,8 +731,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
if (!CSI.empty())
LastFrameDestroy = std::prev(MBBI, CSI.size());

uint64_t StackSize = getStackSizeWithRVVPadding(MF);
uint64_t RealStackSize = StackSize + RVFI->getReservedSpillsSize();
uint64_t RealStackSize = getStackSizeWithRVVPadding(MF);
uint64_t StackSize = RealStackSize - RVFI->getReservedSpillsSize();
uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
uint64_t RVVStackSize = RVFI->getRVVStackSize();

Expand Down Expand Up @@ -897,8 +882,6 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,

if (FrameReg == getFPReg(STI)) {
Offset += StackOffset::getFixed(RVFI->getVarArgsSaveSize());
if (FI >= 0)
Offset -= StackOffset::getFixed(RVFI->getReservedSpillsSize());
// When using FP to access scalable vector objects, we need to minus
// the frame size.
//
Expand Down Expand Up @@ -965,8 +948,7 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
if (MFI.isFixedObjectIndex(FI)) {
assert(!RI->hasStackRealignment(MF) &&
"Can't index across variable sized realign");
Offset += StackOffset::get(getStackSizeWithRVVPadding(MF) +
RVFI->getReservedSpillsSize(),
Offset += StackOffset::get(getStackSizeWithRVVPadding(MF),
RVFI->getRVVStackSize());
} else {
Offset += StackOffset::getFixed(MFI.getStackSize());
Expand Down Expand Up @@ -1243,47 +1225,17 @@ void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
RVFI->setBranchRelaxationScratchFrameIndex(FI);
}

if (MFI.getCalleeSavedInfo().empty() || RVFI->useSaveRestoreLibCalls(MF) ||
RVFI->isPushable(MF)) {
RVFI->setCalleeSavedStackSize(0);
return;
}

unsigned Size = 0;
unsigned Size = RVFI->getReservedSpillsSize();
for (const auto &Info : MFI.getCalleeSavedInfo()) {
int FrameIdx = Info.getFrameIdx();
if (MFI.getStackID(FrameIdx) != TargetStackID::Default)
if (FrameIdx < 0 || MFI.getStackID(FrameIdx) != TargetStackID::Default)
continue;

Size += MFI.getObjectSize(FrameIdx);
}
RVFI->setCalleeSavedStackSize(Size);
}

void RISCVFrameLowering::processFunctionBeforeFrameIndicesReplaced(
MachineFunction &MF, RegScavenger *RS) const {
// Remove CalleeSavedInfo for registers saved by Zcmp or save/restore
// libcalls.
MachineFrameInfo &MFI = MF.getFrameInfo();
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
if (!RVFI->isPushable(MF) && !RVFI->useSaveRestoreLibCalls(MF))
return;
const std::vector<CalleeSavedInfo> &CSIs = MFI.getCalleeSavedInfo();
std::vector<CalleeSavedInfo> NewCSIs;
for (const auto &CSI : CSIs) {
// Skip CSRs that have fake a frame index.
int ReservedFI = 0;
if (TRI->hasReservedSpillSlot(MF, CSI.getReg(), ReservedFI)) {
assert(CSI.getFrameIdx() == ReservedFI &&
"Reserved CSR spill slot frame index mismatch in CSI");
continue;
}
NewCSIs.push_back(CSI);
}
MFI.setCalleeSavedInfo(std::move(NewCSIs));
}

// Not preserve stack space within prologue for outgoing variables when the
// function contains variable size objects or there are vector objects accessed
// by the frame pointer.
Expand Down Expand Up @@ -1403,6 +1355,93 @@ RISCVFrameLowering::getFirstSPAdjustAmount(const MachineFunction &MF) const {
return 0;
}

// Offsets which need to be scale by XLen representing locations of CSRs which
// are given a fixed location by save/restore libcalls or Zcmp Push/Pop.
static const std::pair<MCPhysReg, int8_t> FixedCSRFIMap[] = {
{/*ra*/ RISCV::X1, -1}, {/*s0*/ RISCV::X8, -2},
{/*s1*/ RISCV::X9, -3}, {/*s2*/ RISCV::X18, -4},
{/*s3*/ RISCV::X19, -5}, {/*s4*/ RISCV::X20, -6},
{/*s5*/ RISCV::X21, -7}, {/*s6*/ RISCV::X22, -8},
{/*s7*/ RISCV::X23, -9}, {/*s8*/ RISCV::X24, -10},
{/*s9*/ RISCV::X25, -11}, {/*s10*/ RISCV::X26, -12},
{/*s11*/ RISCV::X27, -13}};

bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
MachineFunction &MF, const TargetRegisterInfo *TRI,
std::vector<CalleeSavedInfo> &CSI, unsigned &MinCSFrameIndex,
unsigned &MaxCSFrameIndex) const {
// Early exit if no callee saved registers are modified!
if (CSI.empty())
return true;

auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();

if (RVFI->isPushable(MF)) {
// Determine how many GPRs we need to push and save it to RVFI.
Register MaxReg = getMaxPushPopReg(MF, CSI);
if (MaxReg != RISCV::NoRegister) {
auto [RegEnc, PushedRegNum] = getPushPopEncodingAndNum(MaxReg);
RVFI->setRVPushRegs(PushedRegNum);
RVFI->setRVPushStackSize(alignTo((STI.getXLen() / 8) * PushedRegNum, 16));

// Use encoded number to represent registers to spill.
RVFI->setRVPushRlist(RegEnc);
}
}

MachineFrameInfo &MFI = MF.getFrameInfo();
const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();

for (auto &CS : CSI) {
unsigned Reg = CS.getReg();
const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
unsigned Size = RegInfo->getSpillSize(*RC);

// This might need a fixed stack slot.
if (RVFI->useSaveRestoreLibCalls(MF) || RVFI->isPushable(MF)) {
const auto *FII = llvm::find_if(
FixedCSRFIMap, [&](auto P) { return P.first == CS.getReg(); });
if (FII != std::end(FixedCSRFIMap)) {
int64_t Offset;
if (RVFI->isPushable(MF))
Offset = -((FII->second + RVFI->getRVPushRegs() + 1) * (int64_t)Size);
else
Offset = FII->second * (int64_t)Size;

int FrameIdx = MFI.CreateFixedSpillStackObject(Size, Offset);
assert(FrameIdx < 0);
CS.setFrameIdx(FrameIdx);
continue;
}
}

// Not a fixed slot.
Align Alignment = RegInfo->getSpillAlign(*RC);
// We may not be able to satisfy the desired alignment specification of
// the TargetRegisterClass if the stack alignment is smaller. Use the
// min.
Alignment = std::min(Alignment, getStackAlign());
int FrameIdx = MFI.CreateStackObject(Size, Alignment, true);
if ((unsigned)FrameIdx < MinCSFrameIndex)
MinCSFrameIndex = FrameIdx;
if ((unsigned)FrameIdx > MaxCSFrameIndex)
MaxCSFrameIndex = FrameIdx;
CS.setFrameIdx(FrameIdx);
}

// Allocate a fixed object that covers the full push or libcall size.
if (RVFI->isPushable(MF)) {
if (int64_t PushSize = RVFI->getRVPushStackSize())
MFI.CreateFixedSpillStackObject(PushSize, -PushSize);
} else if (int LibCallRegs = getLibCallID(MF, CSI) + 1) {
int64_t LibCallFrameSize =
alignTo((STI.getXLen() / 8) * LibCallRegs, getStackAlign());
MFI.CreateFixedSpillStackObject(LibCallFrameSize, -LibCallFrameSize);
}

return true;
}

bool RISCVFrameLowering::spillCalleeSavedRegisters(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
Expand All @@ -1418,14 +1457,10 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
// Emit CM.PUSH with base SPimm & evaluate Push stack
RISCVMachineFunctionInfo *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
if (RVFI->isPushable(*MF)) {
Register MaxReg = getMaxPushPopReg(*MF, CSI);
if (MaxReg != RISCV::NoRegister) {
auto [RegEnc, PushedRegNum] = getPushPopEncodingAndNum(MaxReg);
RVFI->setRVPushRegs(PushedRegNum);
RVFI->setRVPushStackSize(alignTo((STI.getXLen() / 8) * PushedRegNum, 16));

unsigned PushedRegNum = RVFI->getRVPushRegs();
if (PushedRegNum > 0) {
// Use encoded number to represent registers to spill.
RVFI->setRVPushRlist(RegEnc);
int RegEnc = RVFI->getRVPushRlist();
MachineInstrBuilder PushBuilder =
BuildMI(MBB, MI, DL, TII.get(RISCV::CM_PUSH))
.setMIFlag(MachineInstr::FrameSetup);
Expand Down
10 changes: 6 additions & 4 deletions llvm/lib/Target/RISCV/RISCVFrameLowering.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -37,10 +37,6 @@ class RISCVFrameLowering : public TargetFrameLowering {
void processFunctionBeforeFrameFinalized(MachineFunction &MF,
RegScavenger *RS) const override;

void
processFunctionBeforeFrameIndicesReplaced(MachineFunction &MF,
RegScavenger *RS) const override;

bool hasFP(const MachineFunction &MF) const override;

bool hasBP(const MachineFunction &MF) const;
Expand All @@ -49,6 +45,12 @@ class RISCVFrameLowering : public TargetFrameLowering {
MachineBasicBlock::iterator
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const override;

bool assignCalleeSavedSpillSlots(MachineFunction &MF,
const TargetRegisterInfo *TRI,
std::vector<CalleeSavedInfo> &CSI,
unsigned &MinCSFrameIndex,
unsigned &MaxCSFrameIndex) const override;
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
ArrayRef<CalleeSavedInfo> CSI,
Expand Down
34 changes: 0 additions & 34 deletions llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -156,40 +156,6 @@ const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
return CSR_NoRegs_RegMask;
}

// Frame indexes representing locations of CSRs which are given a fixed location
// by save/restore libcalls or Zcmp Push/Pop.
static const std::pair<unsigned, int> FixedCSRFIMap[] = {
{/*ra*/ RISCV::X1, -1},
{/*s0*/ RISCV::X8, -2},
{/*s1*/ RISCV::X9, -3},
{/*s2*/ RISCV::X18, -4},
{/*s3*/ RISCV::X19, -5},
{/*s4*/ RISCV::X20, -6},
{/*s5*/ RISCV::X21, -7},
{/*s6*/ RISCV::X22, -8},
{/*s7*/ RISCV::X23, -9},
{/*s8*/ RISCV::X24, -10},
{/*s9*/ RISCV::X25, -11},
{/*s10*/ RISCV::X26, -12},
{/*s11*/ RISCV::X27, -13}
};

bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
Register Reg,
int &FrameIdx) const {
const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
if (!RVFI->useSaveRestoreLibCalls(MF) && !RVFI->isPushable(MF))
return false;

const auto *FII =
llvm::find_if(FixedCSRFIMap, [&](auto P) { return P.first == Reg; });
if (FII == std::end(FixedCSRFIMap))
return false;

FrameIdx = FII->second;
return true;
}

void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator II,
const DebugLoc &DL, Register DestReg,
Expand Down
3 changes: 0 additions & 3 deletions llvm/lib/Target/RISCV/RISCVRegisterInfo.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -35,9 +35,6 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {

const uint32_t *getNoPreservedMask() const override;

bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg,
int &FrameIdx) const override;

// Update DestReg to have the value SrcReg plus an offset. This is
// used during frame layout, and we may need to ensure that if we
// split the offset internally that the DestReg is always aligned,
Expand Down
Loading