[AMDGPU] Update tests for GFX12 errors and unsupported instructions

[jayfoad]

No description provided.

[llvmbot]

@llvm/pr-subscribers-mc

@llvm/pr-subscribers-backend-amdgpu

Author: Jay Foad (jayfoad)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/77624.diff

2 Files Affected:

• (modified) llvm/test/MC/AMDGPU/gfx12_err.s (+72)
• (modified) llvm/test/MC/AMDGPU/gfx12_unsupported.s (+27)

diff --git a/llvm/test/MC/AMDGPU/gfx12_err.s b/llvm/test/MC/AMDGPU/gfx12_err.s
index b103d7cef97692..edc24f4cf4fe91 100644
--- a/llvm/test/MC/AMDGPU/gfx12_err.s
+++ b/llvm/test/MC/AMDGPU/gfx12_err.s
@@ -1,5 +1,77 @@
 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX12-ERR --implicit-check-not=error: -strict-whitespace %s
 
+v_cubesc_f32_e64_dpp v5, v1, v2, 12345678 row_shr:4 row_mask:0xf bank_mask:0xf
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add3_u32_e64_dpp v5, v1, v2, 49812340 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f32_i32_e64_dpp v5, s1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f32_i32_e64_dpp v5, s1 row_shl:15 row_mask:0xf bank_mask:0xf
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f16_u16_e64_dpp v5, s1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cvt_f16_u16_e64_dpp v5, s1 row_shl:1 row_mask:0xf bank_mask:0xf
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+; disallow space between colons
+v_dual_mul_f32 v0, v0, v2 : : v_dual_mul_f32 v1, v1, v3
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
+
+// On GFX12, v_dot8_i32_i4 is a valid SP3 alias for v_dot8_i32_iu4.
+// However, we intentionally leave it unimplemented because on other
+// processors v_dot8_i32_i4 denotes an instruction of a different
+// behaviour, which is considered potentially dangerous.
+v_dot8_i32_i4 v0, v1, v2, v3
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+// On GFX12, v_dot4_i32_i8 is a valid SP3 alias for v_dot4_i32_iu8.
+// However, we intentionally leave it unimplemented because on other
+// processors v_dot4_i32_i8 denotes an instruction of a different
+// behaviour, which is considered potentially dangerous.
+v_dot4_i32_i8 v0, v1, v2, v3
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+v_dot4c_i32_i8 v0, v1, v2
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+v_cmp_class_f16_e64_dpp s105, s2, v2 row_ror:15
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_class_f32_e64_dpp s1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_fma_mix_f32_e64_dpp v5, s1, v3, v4 quad_perm:[3,2,1,0]
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_fma_mix_f32_e64_dpp v5, v1, s3, v4 quad_perm:[3,2,1,0]
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_fma_mix_f32_e64_dpp v5, s1, v3, v4 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_fma_mix_f32_e64_dpp v5, v1, s3, v4 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_fma_mixhi_f16_e64_dpp v5, v1, 0, v4 quad_perm:[3,2,1,0]
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_fma_mixlo_f16_e64_dpp v5, v1, 1, v4 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_lshlrev_b64 v[5:6], s2, s[0:1]
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
+
+v_lshrrev_b64 v[5:6], s2, s[0:1]
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
+
+v_ashrrev_i64 v[5:6], s2, s[0:1]
+// GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
+
 image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:0x7
 // GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: expected an identifier
 
diff --git a/llvm/test/MC/AMDGPU/gfx12_unsupported.s b/llvm/test/MC/AMDGPU/gfx12_unsupported.s
index aabaf526dc2a86..bf8f7437c04206 100644
--- a/llvm/test/MC/AMDGPU/gfx12_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx12_unsupported.s
@@ -34,6 +34,18 @@ s_cbranch_cdbgsys_or_user 0
 s_cbranch_cdbgsys_and_user 0
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
+v_fmac_legacy_f32 v0, v1, v2
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+v_dot2c_f32_f16 v0, v1, v2
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+v_dual_max_f32 v0, v1, v2 :: v_dual_max_f32 v3, v4, v5
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+v_dual_min_f32 v0, v1, v2 :: v_dual_min_f32 v3, v4, v5
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
 ds_cmpstore_f32 v0, v1, v2
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
@@ -91,6 +103,15 @@ s_cmpk_lt_u32 s0, 0
 s_cmpk_le_u32 s0, 0
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
+buffer_atomic_cmpswap_f32 v[5:6], off, s[96:99], s3
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+flat_atomic_cmpswap_f32 v[5:6], off, s[96:99], s3
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+global_atomic_cmpswap_f32 v[5:6], off, s[96:99], s3
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
 ds_gws_sema_release_all gds
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
@@ -208,6 +229,12 @@ buffer_gl1_inv
 buffer_wbinvl1
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
+flat_atomic_csub v1, v[0:1], v2 offset:64 th:TH_ATOMIC_RETURN
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid instruction
+
+ds_add_f32 v255, v255 offset:4 gds
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: gds modifier is not supported on this GPU
+
 buffer_load_lds_b32 off, s[8:11], s3
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 

[DadSchoorse]

Does GFX12 really not support HasDPPSrc1SGPR unlike GFX11.5?

[jayfoad]

Good question! GFX12 does support HasDPPSrc1SGPR but (a) it is not yet implemented (I will put up a patch for it very soon) and (b) there seems to be some bug where it only works for integer instructions: #67461 (comment)

[jayfoad]

#77929