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DAG: Handle equal size element build_vector promotion #76213

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Merged
merged 1 commit into from
Dec 23, 2023
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DAG: Handle equal size element build_vector promotion #76213

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10 changes: 7 additions & 3 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4908,7 +4908,9 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
static MVT getPromotedVectorElementType(const TargetLowering &TLI,
MVT EltVT, MVT NewEltVT) {
unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
MVT MidVT = OldEltsPerNewElt == 1
? NewEltVT
: MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
assert(TLI.isTypeLegal(MidVT) && "unexpected");
return MidVT;
}
Expand Down Expand Up @@ -5395,7 +5397,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {

assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
"Invalid promote type for build_vector");
assert(NewEltVT.bitsLT(EltVT) && "not handled");
assert(NewEltVT.bitsLE(EltVT) && "not handled");

MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);

Expand All @@ -5406,7 +5408,9 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
}

SDLoc SL(Node);
SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
SDValue Concat =
DAG.getNode(MidVT == NewEltVT ? ISD::BUILD_VECTOR : ISD::CONCAT_VECTORS,
SL, NVT, NewOps);
SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
Results.push_back(CvtVec);
break;
Expand Down