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[ValueTracking] Infer signedness from dom conditions #72049

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[ValueTracking] Infer signedness from dom conditions #72049

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16 changes: 16 additions & 0 deletions llvm/lib/Analysis/ValueTracking.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -290,6 +290,10 @@ bool llvm::isKnownNonNegative(const Value *V, const DataLayout &DL,
unsigned Depth, AssumptionCache *AC,
const Instruction *CxtI, const DominatorTree *DT,
bool UseInstrInfo) {
if (isImpliedByDomCondition(ICmpInst::ICMP_SGE, V,
Constant::getNullValue(V->getType()), CxtI, DL)
.value_or(false))
return true;
KnownBits Known = computeKnownBits(V, DL, Depth, AC, CxtI, DT, UseInstrInfo);
return Known.isNonNegative();
}
Expand All @@ -300,6 +304,10 @@ bool llvm::isKnownPositive(const Value *V, const DataLayout &DL, unsigned Depth,
if (auto *CI = dyn_cast<ConstantInt>(V))
return CI->getValue().isStrictlyPositive();

if (isImpliedByDomCondition(ICmpInst::ICMP_SGT, V,
Constant::getNullValue(V->getType()), CxtI, DL)
.value_or(false))
return true;
// TODO: We'd doing two recursive queries here. We should factor this such
// that only a single query is needed.
return isKnownNonNegative(V, DL, Depth, AC, CxtI, DT, UseInstrInfo) &&
Expand All @@ -309,6 +317,10 @@ bool llvm::isKnownPositive(const Value *V, const DataLayout &DL, unsigned Depth,
bool llvm::isKnownNegative(const Value *V, const DataLayout &DL, unsigned Depth,
AssumptionCache *AC, const Instruction *CxtI,
const DominatorTree *DT, bool UseInstrInfo) {
if (isImpliedByDomCondition(ICmpInst::ICMP_SLT, V,
Constant::getNullValue(V->getType()), CxtI, DL)
.value_or(false))
return true;
KnownBits Known = computeKnownBits(V, DL, Depth, AC, CxtI, DT, UseInstrInfo);
return Known.isNegative();
}
Expand Down Expand Up @@ -3197,6 +3209,10 @@ static bool isKnownNonEqual(const Value *V1, const Value *V2, unsigned Depth,
if (isNonEqualSelect(V1, V2, Depth, Q) || isNonEqualSelect(V2, V1, Depth, Q))
return true;

if (isImpliedByDomCondition(ICmpInst::ICMP_NE, V1, V2, Q.CxtI, Q.DL)
.value_or(false))
return true;

return false;
}

Expand Down
6 changes: 3 additions & 3 deletions llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll
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Expand Up @@ -865,7 +865,7 @@ define i16 @negation_of_zeroext_of_nonnegative(i8 %x) {
; CHECK-NEXT: [[T1:%.*]] = icmp sgt i8 [[T0]], -1
; CHECK-NEXT: br i1 [[T1]], label [[NONNEG_BB:%.*]], label [[NEG_BB:%.*]]
; CHECK: nonneg_bb:
; CHECK-NEXT: [[T2:%.*]] = zext i8 [[T0]] to i16
; CHECK-NEXT: [[T2:%.*]] = zext nneg i8 [[T0]] to i16
; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]]
; CHECK-NEXT: ret i16 [[T3]]
; CHECK: neg_bb:
Expand All @@ -889,7 +889,7 @@ define i16 @negation_of_zeroext_of_positive(i8 %x) {
; CHECK-NEXT: [[T1:%.*]] = icmp sgt i8 [[T0]], 0
; CHECK-NEXT: br i1 [[T1]], label [[NONNEG_BB:%.*]], label [[NEG_BB:%.*]]
; CHECK: nonneg_bb:
; CHECK-NEXT: [[T2:%.*]] = zext i8 [[T0]] to i16
; CHECK-NEXT: [[T2:%.*]] = zext nneg i8 [[T0]] to i16
; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]]
; CHECK-NEXT: ret i16 [[T3]]
; CHECK: neg_bb:
Expand Down Expand Up @@ -961,7 +961,7 @@ define i16 @negation_of_signext_of_nonnegative__wrong_cast(i8 %x) {
; CHECK-NEXT: [[T1:%.*]] = icmp sgt i8 [[T0]], -1
; CHECK-NEXT: br i1 [[T1]], label [[NONNEG_BB:%.*]], label [[NEG_BB:%.*]]
; CHECK: nonneg_bb:
; CHECK-NEXT: [[T2:%.*]] = sext i8 [[T0]] to i16
; CHECK-NEXT: [[T2:%.*]] = zext nneg i8 [[T0]] to i16
; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]]
; CHECK-NEXT: ret i16 [[T3]]
; CHECK: neg_bb:
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/Transforms/InstCombine/sub-of-negatible.ll
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Expand Up @@ -889,7 +889,7 @@ define i16 @negation_of_zeroext_of_nonnegative(i8 %x) {
; CHECK-NEXT: [[T1:%.*]] = icmp sgt i8 [[T0]], -1
; CHECK-NEXT: br i1 [[T1]], label [[NONNEG_BB:%.*]], label [[NEG_BB:%.*]]
; CHECK: nonneg_bb:
; CHECK-NEXT: [[T2:%.*]] = zext i8 [[T0]] to i16
; CHECK-NEXT: [[T2:%.*]] = zext nneg i8 [[T0]] to i16
; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]]
; CHECK-NEXT: ret i16 [[T3]]
; CHECK: neg_bb:
Expand All @@ -913,7 +913,7 @@ define i16 @negation_of_zeroext_of_positive(i8 %x) {
; CHECK-NEXT: [[T1:%.*]] = icmp sgt i8 [[T0]], 0
; CHECK-NEXT: br i1 [[T1]], label [[NONNEG_BB:%.*]], label [[NEG_BB:%.*]]
; CHECK: nonneg_bb:
; CHECK-NEXT: [[T2:%.*]] = zext i8 [[T0]] to i16
; CHECK-NEXT: [[T2:%.*]] = zext nneg i8 [[T0]] to i16
; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]]
; CHECK-NEXT: ret i16 [[T3]]
; CHECK: neg_bb:
Expand Down Expand Up @@ -985,7 +985,7 @@ define i16 @negation_of_signext_of_nonnegative__wrong_cast(i8 %x) {
; CHECK-NEXT: [[T1:%.*]] = icmp sgt i8 [[T0]], -1
; CHECK-NEXT: br i1 [[T1]], label [[NONNEG_BB:%.*]], label [[NEG_BB:%.*]]
; CHECK: nonneg_bb:
; CHECK-NEXT: [[T2:%.*]] = sext i8 [[T0]] to i16
; CHECK-NEXT: [[T2:%.*]] = zext nneg i8 [[T0]] to i16
; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]]
; CHECK-NEXT: ret i16 [[T3]]
; CHECK: neg_bb:
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
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Expand Up @@ -20,11 +20,11 @@ define void @fp_iv_loop1(ptr noalias nocapture %A, i32 %N) #0 {
; AUTO_VEC-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[N:%.*]], 0
; AUTO_VEC-NEXT: br i1 [[CMP4]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]]
; AUTO_VEC: for.body.preheader:
; AUTO_VEC-NEXT: [[ZEXT:%.*]] = zext i32 [[N]] to i64
; AUTO_VEC-NEXT: [[ZEXT:%.*]] = zext nneg i32 [[N]] to i64
; AUTO_VEC-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 32
; AUTO_VEC-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY:%.*]], label [[VECTOR_PH:%.*]]
; AUTO_VEC: vector.ph:
; AUTO_VEC-NEXT: [[N_VEC:%.*]] = and i64 [[ZEXT]], 4294967264
; AUTO_VEC-NEXT: [[N_VEC:%.*]] = and i64 [[ZEXT]], 2147483616
; AUTO_VEC-NEXT: [[DOTCAST:%.*]] = sitofp i64 [[N_VEC]] to float
; AUTO_VEC-NEXT: [[TMP0:%.*]] = fmul fast float [[DOTCAST]], 5.000000e-01
; AUTO_VEC-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP0]], 1.000000e+00
Expand Down Expand Up @@ -103,12 +103,12 @@ define void @fp_iv_loop2(ptr noalias nocapture %A, i32 %N) {
; AUTO_VEC-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[N:%.*]], 0
; AUTO_VEC-NEXT: br i1 [[CMP4]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]]
; AUTO_VEC: for.body.preheader:
; AUTO_VEC-NEXT: [[ZEXT:%.*]] = zext i32 [[N]] to i64
; AUTO_VEC-NEXT: [[ZEXT:%.*]] = zext nneg i32 [[N]] to i64
; AUTO_VEC-NEXT: [[XTRAITER:%.*]] = and i64 [[ZEXT]], 7
; AUTO_VEC-NEXT: [[TMP0:%.*]] = icmp ult i32 [[N]], 8
; AUTO_VEC-NEXT: br i1 [[TMP0]], label [[FOR_END_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_BODY_PREHEADER_NEW:%.*]]
; AUTO_VEC: for.body.preheader.new:
; AUTO_VEC-NEXT: [[UNROLL_ITER:%.*]] = and i64 [[ZEXT]], 4294967288
; AUTO_VEC-NEXT: [[UNROLL_ITER:%.*]] = and i64 [[ZEXT]], 2147483640
; AUTO_VEC-NEXT: br label [[FOR_BODY:%.*]]
; AUTO_VEC: for.body:
; AUTO_VEC-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_7:%.*]], [[FOR_BODY]] ]
Expand Down
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