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[DAGCombiner] Remove most NoSignedZerosFPMath uses #161180

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Merged
merged 2 commits into from
Sep 30, 2025
Merged

[DAGCombiner] Remove most NoSignedZerosFPMath uses #161180

merged 2 commits into from
Sep 30, 2025

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@paperchalice
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@paperchalice paperchalice commented Sep 29, 2025 •
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Remained two uses are related to fneg and foldFPToIntToFP, some AMDGPU tests are duplicated and regenerated.

@paperchalice
[DAGCombiner] Remove most NoSignedZerosFPMath uses
0891cc1 
Remained two uses are related to fneg and foldFPToIntToFP
@paperchalice paperchalice marked this pull request as ready for review September 30, 2025 02:33
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llvmbot commented Sep 30, 2025 •
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@llvm/pr-subscribers-llvm-selectiondag
@llvm/pr-subscribers-backend-amdgpu

@llvm/pr-subscribers-backend-nvptx

Author: None (paperchalice)

Changes

Remained two uses are related to fneg and foldFPToIntToFP

Patch is 215.66 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/161180.diff

10 Files Affected:

  • (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+4-9)
  • (modified) llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll (+723-698)
  • (modified) llvm/test/CodeGen/AMDGPU/fmax_legacy.ll (+179-47)
  • (modified) llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll (+201-80)
  • (modified) llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll (+723-698)
  • (modified) llvm/test/CodeGen/AMDGPU/fmin_legacy.ll (+227-75)
  • (modified) llvm/test/CodeGen/NVPTX/bug22322.ll (+3-3)
  • (modified) llvm/test/CodeGen/PowerPC/scalar-min-max.ll (+90-142)
  • (modified) llvm/test/CodeGen/VE/Scalar/max.ll (+80-96)
  • (modified) llvm/test/CodeGen/VE/Scalar/min.ll (+80-98)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 77df4b4598c48..204e1f0c75e00 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -11849,9 +11849,7 @@ static bool isLegalToCombineMinNumMaxNum(SelectionDAG &DAG, SDValue LHS,
   if (!VT.isFloatingPoint())
     return false;
 
-  const TargetOptions &Options = DAG.getTarget().Options;
-
-  return (Flags.hasNoSignedZeros() || Options.NoSignedZerosFPMath) &&
+  return Flags.hasNoSignedZeros() &&
          TLI.isProfitableToCombineMinNumMaxNum(VT) &&
          (Flags.hasNoNaNs() ||
           (DAG.isKnownNeverNaN(RHS) && DAG.isKnownNeverNaN(LHS)));
@@ -17351,7 +17349,7 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) {
   // Always prefer FMAD to FMA for precision.
   unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
   bool Aggressive = TLI.enableAggressiveFMAFusion(VT);
-  bool NoSignedZero = Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros();
+  bool NoSignedZero = Flags.hasNoSignedZeros();
 
   // Is the node an FMUL and contractable either due to global flags or
   // SDNodeFlags.
@@ -18327,11 +18325,9 @@ template <class MatchContextClass> SDValue DAGCombiner::visitFMA(SDNode *N) {
       return matcher.getNode(ISD::FMA, DL, VT, NegN0, NegN1, N2);
   }
 
-  // FIXME: use fast math flags instead of Options.UnsafeFPMath
-  // TODO: Finally migrate away from global TargetOptions.
   if ((Options.NoNaNsFPMath && Options.NoInfsFPMath) ||
       (N->getFlags().hasNoNaNs() && N->getFlags().hasNoInfs())) {
-    if (Options.NoSignedZerosFPMath || N->getFlags().hasNoSignedZeros() ||
+    if (N->getFlags().hasNoSignedZeros() ||
         (N2CFP && !N2CFP->isExactlyValue(-0.0))) {
       if (N0CFP && N0CFP->isZero())
         return N2;
@@ -18636,8 +18632,7 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) {
   }
 
   // Fold X/Sqrt(X) -> Sqrt(X)
-  if ((Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) &&
-      Flags.hasAllowReassociation())
+  if (Flags.hasNoSignedZeros() && Flags.hasAllowReassociation())
     if (N1.getOpcode() == ISD::FSQRT && N0 == N1.getOperand(0))
       return N1;
 
diff --git a/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll b/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
index ed48999e6d1e7..bd28f72bb8913 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
@@ -1,734 +1,759 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-SAFE %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-NNAN %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s
 
-; RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefix=VI-SAFE %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=VI-NNAN %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefix=VI %s
 
-; RUN: llc -mtriple=amdgcn-- < %s | FileCheck -enable-var-scope -check-prefix=SI-SAFE %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- < %s | FileCheck -enable-var-scope -check-prefixes=SI-NNAN %s
+; RUN: llc -mtriple=amdgcn-- < %s | FileCheck -enable-var-scope -check-prefix=SI %s
 
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-SAFE-TRUE16 %s
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-SAFE-FAKE16 %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-NNAN,GFX11-NNAN-TRUE16 %s
-; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-NNAN,GFX11-NNAN-FAKE16 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s
 
 define half @test_fmax_legacy_ugt_f16(half %a, half %b) #0 {
-; GFX9-SAFE-LABEL: test_fmax_legacy_ugt_f16:
-; GFX9-SAFE:       ; %bb.0:
-; GFX9-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SAFE-NEXT:    v_cmp_nle_f16_e32 vcc, v0, v1
-; GFX9-SAFE-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX9-SAFE-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-NNAN-LABEL: test_fmax_legacy_ugt_f16:
-; GFX9-NNAN:       ; %bb.0:
-; GFX9-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NNAN-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX9-NNAN-NEXT:    s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: test_fmax_legacy_ugt_f16:
-; VI-SAFE:       ; %bb.0:
-; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT:    v_cmp_nle_f16_e32 vcc, v0, v1
-; VI-SAFE-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
-; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]
-;
-; VI-NNAN-LABEL: test_fmax_legacy_ugt_f16:
-; VI-NNAN:       ; %bb.0:
-; VI-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NNAN-NEXT:    v_max_f16_e32 v0, v0, v1
-; VI-NNAN-NEXT:    s_setpc_b64 s[30:31]
-;
-; SI-SAFE-LABEL: test_fmax_legacy_ugt_f16:
-; SI-SAFE:       ; %bb.0:
-; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v0, v1, v0
-; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]
-;
-; SI-NNAN-LABEL: test_fmax_legacy_ugt_f16:
-; SI-NNAN:       ; %bb.0:
-; SI-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; SI-NNAN-NEXT:    v_max_f32_e32 v0, v0, v1
-; SI-NNAN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-TRUE16-LABEL: test_fmax_legacy_ugt_f16:
-; GFX11-SAFE-TRUE16:       ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: test_fmax_legacy_ugt_f16:
-; GFX11-SAFE-FAKE16:       ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0, v1
-; GFX11-SAFE-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-NNAN-TRUE16-LABEL: test_fmax_legacy_ugt_f16:
-; GFX11-NNAN-TRUE16:       ; %bb.0:
-; GFX11-NNAN-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NNAN-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v1.l
-; GFX11-NNAN-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-NNAN-FAKE16-LABEL: test_fmax_legacy_ugt_f16:
-; GFX11-NNAN-FAKE16:       ; %bb.0:
-; GFX11-NNAN-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NNAN-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX11-NNAN-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_fmax_legacy_ugt_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_cmp_nle_f16_e32 vcc, v0, v1
+; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmax_legacy_ugt_f16:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_cmp_nle_f16_e32 vcc, v0, v1
+; VI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmax_legacy_ugt_f16:
+; SI:       ; %bb.0:
+; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT:    v_max_legacy_f32_e32 v0, v1, v0
+; SI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp ugt half %a, %b
   %val = select i1 %cmp, half %a, half %b
   ret half %val
 }
 
+define half @test_fmax_legacy_ugt_f16_fast(half %a, half %b) #0 {
+; GFX9-LABEL: test_fmax_legacy_ugt_f16_fast:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmax_legacy_ugt_f16_fast:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_max_f16_e32 v0, v0, v1
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmax_legacy_ugt_f16_fast:
+; SI:       ; %bb.0:
+; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT:    v_max_f32_e32 v0, v0, v1
+; SI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_f16_fast:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_max_f16_e32 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_f16_fast:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
+  %cmp = fcmp ugt half %a, %b
+  %val = select nnan nsz i1 %cmp, half %a, half %b
+  ret half %val
+}
+
 define <2 x half> @test_fmax_legacy_ugt_v2f16(<2 x half> %a, <2 x half> %b) #0 {
-; GFX9-SAFE-LABEL: test_fmax_legacy_ugt_v2f16:
-; GFX9-SAFE:       ; %bb.0:
-; GFX9-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SAFE-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX9-SAFE-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX9-SAFE-NEXT:    v_cmp_nle_f16_e32 vcc, v3, v2
-; GFX9-SAFE-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX9-SAFE-NEXT:    v_cmp_nle_f16_e32 vcc, v0, v1
-; GFX9-SAFE-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX9-SAFE-NEXT:    s_mov_b32 s4, 0x5040100
-; GFX9-SAFE-NEXT:    v_perm_b32 v0, v2, v0, s4
-; GFX9-SAFE-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-NNAN-LABEL: test_fmax_legacy_ugt_v2f16:
-; GFX9-NNAN:       ; %bb.0:
-; GFX9-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NNAN-NEXT:    v_pk_max_f16 v0, v0, v1
-; GFX9-NNAN-NEXT:    s_setpc_b64 s[30:31]
-;
-; VI-SAFE-LABEL: test_fmax_legacy_ugt_v2f16:
-; VI-SAFE:       ; %bb.0:
-; VI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SAFE-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; VI-SAFE-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; VI-SAFE-NEXT:    v_cmp_nle_f16_e32 vcc, v3, v2
-; VI-SAFE-NEXT:    v_cndmask_b32_sdwa v2, v2, v3, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-SAFE-NEXT:    v_cmp_nle_f16_e32 vcc, v0, v1
-; VI-SAFE-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
-; VI-SAFE-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-SAFE-NEXT:    s_setpc_b64 s[30:31]
-;
-; VI-NNAN-LABEL: test_fmax_legacy_ugt_v2f16:
-; VI-NNAN:       ; %bb.0:
-; VI-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NNAN-NEXT:    v_max_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-NNAN-NEXT:    v_max_f16_e32 v0, v0, v1
-; VI-NNAN-NEXT:    v_or_b32_e32 v0, v0, v2
-; VI-NNAN-NEXT:    s_setpc_b64 s[30:31]
-;
-; SI-SAFE-LABEL: test_fmax_legacy_ugt_v2f16:
-; SI-SAFE:       ; %bb.0:
-; SI-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; SI-SAFE-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v3, v3
-; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; SI-SAFE-NEXT:    v_cvt_f32_f16_e32 v2, v2
-; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v0, v2, v0
-; SI-SAFE-NEXT:    v_max_legacy_f32_e32 v1, v3, v1
-; SI-SAFE-NEXT:    s_setpc_b64 s[30:31]
-;
-; SI-NNAN-LABEL: test_fmax_legacy_ugt_v2f16:
-; SI-NNAN:       ; %bb.0:
-; SI-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; SI-NNAN-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v3, v3
-; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v2, v2
-; SI-NNAN-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; SI-NNAN-NEXT:    v_max_f32_e32 v0, v0, v2
-; SI-NNAN-NEXT:    v_max_f32_e32 v1, v1, v3
-; SI-NNAN-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-TRUE16-LABEL: test_fmax_legacy_ugt_v2f16:
-; GFX11-SAFE-TRUE16:       ; %bb.0:
-; GFX11-SAFE-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-TRUE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0.h, v1.h
-; GFX11-SAFE-TRUE16-NEXT:    v_cmp_nle_f16_e64 s0, v0.l, v1.l
-; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
-; GFX11-SAFE-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX11-SAFE-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX11-SAFE-TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-FAKE16-LABEL: test_fmax_legacy_ugt_v2f16:
-; GFX11-SAFE-FAKE16:       ; %bb.0:
-; GFX11-SAFE-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-SAFE-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-SAFE-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-SAFE-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v3, v2
-; GFX11-SAFE-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0, v1
-; GFX11-SAFE-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-SAFE-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-SAFE-FAKE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-NNAN-LABEL: test_fmax_legacy_ugt_v2f16:
-; GFX11-NNAN:       ; %bb.0:
-; GFX11-NNAN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NNAN-NEXT:    v_pk_max_f16 v0, v0, v1
-; GFX11-NNAN-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: test_fmax_legacy_ugt_v2f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX9-NEXT:    v_cmp_nle_f16_e32 vcc, v3, v2
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX9-NEXT:    v_cmp_nle_f16_e32 vcc, v0, v1
+; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX9-NEXT:    s_mov_b32 s4, 0x5040100
+; GFX9-NEXT:    v_perm_b32 v0, v2, v0, s4
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmax_legacy_ugt_v2f16:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; VI-NEXT:    v_cmp_nle_f16_e32 vcc, v3, v2
+; VI-NEXT:    v_cndmask_b32_sdwa v2, v2, v3, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT:    v_cmp_nle_f16_e32 vcc, v0, v1
+; VI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
+; VI-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmax_legacy_ugt_v2f16:
+; SI:       ; %bb.0:
+; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT:    v_max_legacy_f32_e32 v0, v2, v0
+; SI-NEXT:    v_max_legacy_f32_e32 v1, v3, v1
+; SI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_v2f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0.h, v1.h
+; GFX11-TRUE16-NEXT:    v_cmp_nle_f16_e64 s0, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_v2f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v3, v2
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_nle_f16_e32 vcc_lo, v0, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
   %cmp = fcmp ugt <2 x half> %a, %b
   %val = select <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
   ret <2 x half> %val
 }
 
+define <2 x half> @test_fmax_legacy_ugt_v2f16_fast(<2 x half> %a, <2 x half> %b) #0 {
+; GFX9-LABEL: test_fmax_legacy_ugt_v2f16_fast:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_pk_max_f16 v0, v0, v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; VI-LABEL: test_fmax_legacy_ugt_v2f16_fast:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_max_f16_sdwa v2, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT:    v_max_f16_e32 v0, v0, v1
+; VI-NEXT:    v_or_b32_e32 v0, v0, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; SI-LABEL: test_fmax_legacy_ugt_v2f16_fast:
+; SI:       ; %bb.0:
+; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT:    v_max_f32_e32 v0, v0, v2
+; SI-NEXT:    v_max_f32_e32 v1, v1, v3
+; SI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: test_fmax_legacy_ugt_v2f16_fast:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_pk_max_f16 v0, v0, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %cmp = fcmp ugt <2 x half> %a, %b
+  %val = select nnan nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
+  ret <2 x half> %val
+}
+
 define <3 x half> @test_fmax_legacy_ugt_v3f16(<3 x half> %a, <3 x half> %b) #0 {
-; GFX9-SAFE-LABEL: test_fmax_legacy_ugt_v3f16:
-; GFX9-SAFE:       ; %bb.0:
-; GFX9-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-SAFE-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
-; GFX9-SAFE-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
-; GFX9-SAFE-NEXT:    v_cmp_nle_f16_e32 vcc, v5, v4
...
[truncated]

@arsenm arsenm added the floating-point Floating-point math label Sep 30, 2025
@paperchalice paperchalice merged commit c6d3b51 into llvm:main Sep 30, 2025
16 checks passed
@paperchalice paperchalice deleted the nsz-most branch September 30, 2025 04:53
mahesh-attarde pushed a commit to mahesh-attarde/llvm-project that referenced this pull request Oct 3, 2025
@paperchalice @mahesh-attarde
[DAGCombiner] Remove most NoSignedZerosFPMath uses (llvm#161180)
d038394 
Remained two uses are related to fneg and foldFPToIntToFP, some AMDGPU
tests are duplicated and regenerated.
@aemerson aemerson mentioned this pull request Oct 16, 2025
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backend:AMDGPU backend:NVPTX backend:PowerPC floating-point Floating-point math llvm:SelectionDAG SelectionDAGISel as well

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