Skip to content

[Docs][RISCV]Remove experimental from Smctr, Ssctr,Sdext and Sdtrig #161058

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Sep 30, 2025
Merged

[Docs][RISCV]Remove experimental from Smctr, Ssctr,Sdext and Sdtrig #161058

Changes from 2 commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
a348874
[Docs][RISCV]Remove experimental from Smctr, Ssctr,Sdext and Sdtrig
ChunyuLiao Sep 28, 2025
351f73e
add spec docs
ChunyuLiao Sep 30, 2025
796373e
delete Smctr Ssctr spec
ChunyuLiao Sep 30, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
15 changes: 9 additions & 6 deletions llvm/docs/RISCVUsage.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -120,6 +120,8 @@ on support follow.
``H`` Assembly Support
``M`` Supported
``Q`` Assembly Support
``Sdext`` Assembly Support (`See note <#riscv-extensions-specifications-note>`__)
``Sdtrig`` Assembly Support (`See note <#riscv-extensions-specifications-note>`__)
``Sha`` Supported
``Shcounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Shgatpa`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
Expand All @@ -132,6 +134,7 @@ on support follow.
``Smcdeleg`` Supported
``Smcntrpmf`` Supported
``Smcsrind`` Supported
``Smctr`` Assembly Support (`See note <#riscv-extensions-specifications-note>`__)
``Smdbltrp`` Supported
``Smepmp`` Supported
``Smmpm`` Supported
Expand All @@ -144,6 +147,7 @@ on support follow.
``Sscofpmf`` Assembly Support
``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Sscsrind`` Supported
``Ssctr`` Assembly Support (`See note <#riscv-extensions-specifications-note>`__)
``Ssdbltrp`` Supported
``Ssnpm`` Supported
``Sspm`` Supported
Expand Down Expand Up @@ -306,6 +310,11 @@ Supported
``Za128rs``, ``Za64rs``, ``Zama16b``, ``Zic64b``, ``Ziccamoa``, ``Ziccamoc``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare``
These extensions are defined as part of the `RISC-V Profiles specification <https://github.com/riscv/riscv-profiles/releases/tag/v1.0>`__. They do not introduce any new features themselves, but instead describe existing hardware features.

.. _riscv-extensions-specifications-note:

``Sdext``, ``Sdtrig`` `The RISC-V Debug Specification <https://github.com/riscv/riscv-debug-spec/releases/download/1.0/riscv-debug-specification.pdf>`__.
``Smctr``, ``Ssctr`` `RISC-V Control Transfer Records <https://github.com/riscv/riscv-control-transfer-records/releases/download/v1.0_rc3/riscv-ctr-v1.0_rc3.pdf>`__.
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Smctr and Ssctr have been integrated into the riscv-isa-manual I think.

Copy link
Member Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

delete Smctr and Ssctr spec.


.. _riscv-zacas-note:

``Zacas``
Expand Down Expand Up @@ -337,12 +346,6 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zvbc32e``, ``experimental-zvkgs``
LLVM implements the `0.7 release specification <https://github.com/user-attachments/files/16450464/riscv-crypto-spec-vector-extra_v0.0.7.pdf>`__.

``experimental-sdext``, ``experimental-sdtrig``
LLVM implements the `1.0-rc4 specification <https://github.com/riscv/riscv-debug-spec/releases/download/1.0.0-rc4/riscv-debug-specification.pdf>`__.

``experimental-smctr``, ``experimental-ssctr``
LLVM implements the `1.0-rc3 specification <https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3>`__.

``experimental-svukte``
LLVM implements the `0.3 draft specification <https://github.com/riscv/riscv-isa-manual/pull/1564>`__.

Expand Down
Loading