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[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores #157640

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Sep 10, 2025
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[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores #157640

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5 changes: 0 additions & 5 deletions llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2655,11 +2655,6 @@ bool SIGfx12CacheControl::finalizeStore(MachineInstr &MI, bool Atomic) const {
return Changed;
}

// GFX12.5 only: Require SCOPE_SE on stores that may hit the scratch address
// space.
if (TII->mayAccessScratchThroughFlat(MI) && Scope == CPol::SCOPE_CU)
return setScope(MI, CPol::SCOPE_SE);

return Changed;
}

Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
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Expand Up @@ -73,7 +73,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, doub
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
Expand Down Expand Up @@ -192,7 +192,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inreg
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
Expand Down Expand Up @@ -311,7 +311,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, d
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
Expand Down Expand Up @@ -429,7 +429,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inr
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
Expand Down Expand Up @@ -547,7 +547,7 @@ define amdgpu_ps void @raw_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, doub
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
Expand Down Expand Up @@ -666,7 +666,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inreg
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
Expand Down Expand Up @@ -785,7 +785,7 @@ define amdgpu_ps void @struct_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, d
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
Expand Down Expand Up @@ -903,7 +903,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inr
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_min_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
Expand Down Expand Up @@ -1021,7 +1021,7 @@ define amdgpu_ps void @raw_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, doub
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
Expand Down Expand Up @@ -1140,7 +1140,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inreg
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
Expand Down Expand Up @@ -1259,7 +1259,7 @@ define amdgpu_ps void @struct_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, d
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
Expand Down Expand Up @@ -1377,7 +1377,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inr
; GFX1250: ; %bb.0: ; %main_body
; GFX1250-NEXT: buffer_atomic_max_num_f64 v[0:1], v2, s[0:3], null idxen th:TH_ATOMIC_RETURN
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1] scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b64 v[0:1], v[0:1]
; GFX1250-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
Expand Down
28 changes: 14 additions & 14 deletions llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
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Expand Up @@ -572,7 +572,7 @@ define double @flat_system_atomic_fadd_f64(ptr %ptr, double %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_add_f64_e32 v[0:1], v[4:5], v[2:3]
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB34_5: ; %Flow1
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s1
Expand Down Expand Up @@ -634,7 +634,7 @@ define double @flat_one_as_atomic_fadd_f64(ptr %ptr, double %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_add_f64_e32 v[0:1], v[4:5], v[2:3]
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB35_5: ; %Flow1
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s1
Expand Down Expand Up @@ -714,7 +714,7 @@ define double @flat_system_atomic_fmin_f64(ptr %ptr, double %val) {
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB38_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
Expand Down Expand Up @@ -758,7 +758,7 @@ define double @flat_one_as_atomic_fmin_f64(ptr %ptr, double %val) {
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
; GFX1250-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB39_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
Expand Down Expand Up @@ -826,7 +826,7 @@ define double @flat_system_atomic_fmax_f64(ptr %ptr, double %val) {
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB42_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
Expand Down Expand Up @@ -870,7 +870,7 @@ define double @flat_one_as_atomic_fmax_f64(ptr %ptr, double %val) {
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[4:5], v[4:5]
; GFX1250-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[2:3]
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB43_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
Expand Down Expand Up @@ -1009,7 +1009,7 @@ define i64 @flat_one_as_atomic_min_i64(ptr %ptr, i64 %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_min_i64 v[0:1], v[4:5], v[2:3]
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB52_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
Expand Down Expand Up @@ -1052,7 +1052,7 @@ define i64 @flat_system_atomic_min_i64(ptr %ptr, i64 %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_min_i64 v[0:1], v[4:5], v[2:3]
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB53_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
Expand Down Expand Up @@ -1095,7 +1095,7 @@ define i64 @flat_one_as_atomic_max_i64(ptr %ptr, i64 %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_max_i64 v[0:1], v[4:5], v[2:3]
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB54_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
Expand Down Expand Up @@ -1138,7 +1138,7 @@ define i64 @flat_system_atomic_max_i64(ptr %ptr, i64 %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_max_i64 v[0:1], v[4:5], v[2:3]
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB55_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
Expand Down Expand Up @@ -1181,7 +1181,7 @@ define i64 @flat_one_as_atomic_umin_i64(ptr %ptr, i64 %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_min_u64 v[0:1], v[4:5], v[2:3]
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB56_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
Expand Down Expand Up @@ -1224,7 +1224,7 @@ define i64 @flat_system_atomic_umin_i64(ptr %ptr, i64 %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_min_u64 v[0:1], v[4:5], v[2:3]
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB57_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
Expand Down Expand Up @@ -1267,7 +1267,7 @@ define i64 @flat_one_as_atomic_umax_i64(ptr %ptr, i64 %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_max_u64 v[0:1], v[4:5], v[2:3]
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB58_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
Expand Down Expand Up @@ -1310,7 +1310,7 @@ define i64 @flat_system_atomic_umax_i64(ptr %ptr, i64 %val) {
; GFX1250-NEXT: scratch_load_b64 v[4:5], v6, off
; GFX1250-NEXT: s_wait_loadcnt 0x0
; GFX1250-NEXT: v_max_u64 v[0:1], v[4:5], v[2:3]
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off scope:SCOPE_SE
; GFX1250-NEXT: scratch_store_b64 v6, v[0:1], off
; GFX1250-NEXT: .LBB59_4: ; %atomicrmw.phi
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: s_or_b32 exec_lo, exec_lo, s0
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -344,7 +344,7 @@ define amdgpu_ps void @fptrunc_f32_to_bf16(float %a, ptr %out) {
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX1250-NEXT: flat_store_b16 v[2:3], v0 scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b16 v[2:3], v0
; GFX1250-NEXT: s_endpgm
entry:
%a.cvt = fptrunc float %a to bfloat
Expand Down Expand Up @@ -380,7 +380,7 @@ define amdgpu_ps void @fptrunc_f32_to_bf16_abs(float %a, ptr %out) {
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, |v0|, s0
; GFX1250-NEXT: flat_store_b16 v[2:3], v0 scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b16 v[2:3], v0
; GFX1250-NEXT: s_endpgm
entry:
%a.abs = call float @llvm.fabs.f32(float %a)
Expand Down Expand Up @@ -417,7 +417,7 @@ define amdgpu_ps void @fptrunc_f32_to_bf16_neg(float %a, ptr %out) {
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, -v0, s0
; GFX1250-NEXT: flat_store_b16 v[2:3], v0 scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b16 v[2:3], v0
; GFX1250-NEXT: s_endpgm
entry:
%a.neg = fneg float %a
Expand Down Expand Up @@ -480,7 +480,7 @@ define amdgpu_ps void @fptrunc_f64_to_bf16(double %a, ptr %out) {
; GFX1250-NEXT: s_or_b32 vcc_lo, vcc_lo, s0
; GFX1250-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX1250-NEXT: flat_store_b16 v[2:3], v0 scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b16 v[2:3], v0
; GFX1250-NEXT: s_endpgm
entry:
%a.cvt = fptrunc double %a to bfloat
Expand Down Expand Up @@ -543,7 +543,7 @@ define amdgpu_ps void @fptrunc_f64_to_bf16_neg(double %a, ptr %out) {
; GFX1250-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX1250-NEXT: flat_store_b16 v[2:3], v0 scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b16 v[2:3], v0
; GFX1250-NEXT: s_endpgm
entry:
%a.neg = fneg double %a
Expand Down Expand Up @@ -607,7 +607,7 @@ define amdgpu_ps void @fptrunc_f64_to_bf16_abs(double %a, ptr %out) {
; GFX1250-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX1250-NEXT: flat_store_b16 v[2:3], v0 scope:SCOPE_SE
; GFX1250-NEXT: flat_store_b16 v[2:3], v0
; GFX1250-NEXT: s_endpgm
entry:
%a.abs = call double @llvm.fabs.f64(double %a)
Expand Down
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