AMDGPU: Change FLAT classes to use RegisterOperand parameters #156581
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@llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) ChangesThis will make it easier to precisely express operand constraints Patch is 48.54 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/156581.diff 2 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index 19f95c5ac4c37..2bbd4dde7df6e 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -215,11 +215,10 @@ class GlobalSaddrTable <bit is_saddr, string Name = ""> {
// same encoding value as exec_hi, so it isn't possible to use that if
// saddr is 32-bit (which isn't handled here yet).
class FLAT_Load_Pseudo<
- string opName, RegisterClass regClass, bit HasTiedOutput = 0,
+ string opName, RegisterOperand vdata_op, bit HasTiedOutput = 0,
bit HasSaddr = 0, bit EnableSaddr = 0>
: FLAT_Pseudo<opName, (outs), (ins), ""> {
- defvar vdata_op = getLdStRegisterOperand<regClass>.ret;
let OutOperandList = (outs vdata_op:$vdst);
let InOperandList = !con(
!if(EnableSaddr,
@@ -242,7 +241,7 @@ class FLAT_Load_Pseudo<
let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
}
-multiclass FLAT_Flat_Load_Pseudo<string opName, RegisterClass regClass, bit HasTiedInput = 0> {
+multiclass FLAT_Flat_Load_Pseudo<string opName, RegisterOperand regClass = AVLdSt_32, bit HasTiedInput = 0> {
def "" : FLAT_Load_Pseudo<opName, regClass, HasTiedInput>,
GlobalSaddrTable<0, opName>;
let OtherPredicates = [HasFlatGVSMode] in
@@ -251,19 +250,19 @@ multiclass FLAT_Flat_Load_Pseudo<string opName, RegisterClass regClass, bit HasT
}
multiclass FLAT_Flat_Load_Pseudo_t16<string opName> {
- defm "" : FLAT_Flat_Load_Pseudo<opName, VGPR_32, 1>;
+ defm "" : FLAT_Flat_Load_Pseudo<opName, AVLdSt_32, 1>;
let True16Predicate = UseRealTrue16Insts in
- defm _t16 : FLAT_Flat_Load_Pseudo<opName#"_t16", VGPR_16>, True16D16Table<NAME#"_HI", NAME>;
+ defm _t16 : FLAT_Flat_Load_Pseudo<opName#"_t16", VGPROp_16>, True16D16Table<NAME#"_HI", NAME>;
}
-class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
+class FLAT_Store_Pseudo <string opName, RegisterOperand vdataClass,
bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
opName,
(outs),
!con(
!if(EnableSaddr,
- (ins VGPR_32:$vaddr, getLdStRegisterOperand<vdataClass>.ret:$vdata, SReg_64_XEXEC_XNULL:$saddr),
- (ins VReg_64:$vaddr, getLdStRegisterOperand<vdataClass>.ret:$vdata)),
+ (ins VGPR_32:$vaddr, vdataClass:$vdata, SReg_64_XEXEC_XNULL:$saddr),
+ (ins VReg_64:$vaddr, vdataClass:$vdata)),
(ins flat_offset:$offset, CPol_0:$cpol)),
" $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$cpol"> {
let mayLoad = 0;
@@ -273,7 +272,7 @@ class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
let enabled_saddr = EnableSaddr;
}
-multiclass FLAT_Flat_Store_Pseudo<string opName, RegisterClass regClass> {
+multiclass FLAT_Flat_Store_Pseudo<string opName, RegisterOperand regClass = AVLdSt_32> {
def "" : FLAT_Store_Pseudo<opName, regClass>,
GlobalSaddrTable<0, opName>;
let OtherPredicates = [HasFlatGVSMode] in
@@ -282,20 +281,21 @@ multiclass FLAT_Flat_Store_Pseudo<string opName, RegisterClass regClass> {
}
multiclass FLAT_Flat_Store_Pseudo_t16<string opName> {
- defm "" : FLAT_Flat_Store_Pseudo<opName, VGPR_32>;
+ defm "" : FLAT_Flat_Store_Pseudo<opName, AVLdSt_32>;
defvar Name16 = opName#"_t16";
let OtherPredicates = [HasFlatGVSMode, HasTrue16BitInsts] in {
- def _t16 : FLAT_Store_Pseudo<Name16, VGPR_16, 1>,
+ def _t16 : FLAT_Store_Pseudo<Name16, VGPROp_16, 1>,
GlobalSaddrTable<0, Name16>,
True16D16Table<NAME#"_D16_HI", NAME>;
- def _SADDR_t16 : FLAT_Store_Pseudo<Name16, VGPR_16, 1, 1>,
+ def _SADDR_t16 : FLAT_Store_Pseudo<Name16, VGPROp_16, 1, 1>,
GlobalSaddrTable<1, Name16>,
True16D16Table<NAME#"_D16_HI_SADDR", NAME#"_SADDR">;
}
}
-multiclass FLAT_Global_Load_Pseudo<string opName, RegisterClass regClass, bit HasTiedInput = 0> {
+multiclass FLAT_Global_Load_Pseudo<string opName, RegisterOperand regClass = AVLdSt_32,
+ bit HasTiedInput = 0> {
let is_flat_global = 1 in {
def "" : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1>,
GlobalSaddrTable<0, opName>;
@@ -305,21 +305,21 @@ multiclass FLAT_Global_Load_Pseudo<string opName, RegisterClass regClass, bit Ha
}
multiclass FLAT_Global_Load_Pseudo_t16<string opName> {
- defm "" : FLAT_Global_Load_Pseudo<opName, VGPR_32, 1>;
+ defm "" : FLAT_Global_Load_Pseudo<opName, AVLdSt_32, 1>;
defvar Name16 = opName#"_t16";
let OtherPredicates = [HasTrue16BitInsts],
SubtargetPredicate = HasFlatGlobalInsts, is_flat_global = 1 in {
- def _t16 : FLAT_Load_Pseudo<Name16, VGPR_16, 0, 1>,
+ def _t16 : FLAT_Load_Pseudo<Name16, VGPROp_16, 0, 1>,
GlobalSaddrTable<0, Name16>,
True16D16Table<NAME#"_HI", NAME>;
- def _SADDR_t16 : FLAT_Load_Pseudo<Name16, VGPR_16, 0, 1, 1>,
+ def _SADDR_t16 : FLAT_Load_Pseudo<Name16, VGPROp_16, 0, 1, 1>,
GlobalSaddrTable<1, Name16>,
True16D16Table<NAME#"_HI_SADDR", NAME#"_SADDR">;
}
}
-class FLAT_Global_Load_AddTid_Pseudo <string opName, RegisterClass regClass,
+class FLAT_Global_Load_AddTid_Pseudo <string opName, RegisterOperand regClass,
bit HasTiedOutput = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
opName,
(outs regClass:$vdst),
@@ -337,7 +337,7 @@ class FLAT_Global_Load_AddTid_Pseudo <string opName, RegisterClass regClass,
let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
}
-multiclass FLAT_Global_Load_AddTid_Pseudo<string opName, RegisterClass regClass,
+multiclass FLAT_Global_Load_AddTid_Pseudo<string opName, RegisterOperand regClass,
bit HasTiedOutput = 0> {
def "" : FLAT_Global_Load_AddTid_Pseudo<opName, regClass, HasTiedOutput>,
GlobalSaddrTable<0, opName>;
@@ -345,7 +345,7 @@ multiclass FLAT_Global_Load_AddTid_Pseudo<string opName, RegisterClass regClass,
GlobalSaddrTable<1, opName>;
}
-multiclass FLAT_Global_Store_Pseudo<string opName, RegisterClass regClass> {
+multiclass FLAT_Global_Store_Pseudo<string opName, RegisterOperand regClass = AVLdSt_32> {
let is_flat_global = 1 in {
def "" : FLAT_Store_Pseudo<opName, regClass, 1>,
GlobalSaddrTable<0, opName>;
@@ -355,15 +355,15 @@ multiclass FLAT_Global_Store_Pseudo<string opName, RegisterClass regClass> {
}
multiclass FLAT_Global_Store_Pseudo_t16<string opName> {
- defm "" : FLAT_Global_Store_Pseudo<opName, VGPR_32>;
+ defm "" : FLAT_Global_Store_Pseudo<opName, AVLdSt_32>;
defvar Name16 = opName#"_t16";
let OtherPredicates = [HasTrue16BitInsts],
SubtargetPredicate = HasFlatGlobalInsts, is_flat_global = 1 in {
- def _t16 : FLAT_Store_Pseudo<Name16, VGPR_16, 1>,
+ def _t16 : FLAT_Store_Pseudo<Name16, VGPROp_16, 1>,
GlobalSaddrTable<0, Name16>,
True16D16Table<NAME#"_D16_HI", NAME>;
- def _SADDR_t16 : FLAT_Store_Pseudo<Name16, VGPR_16, 1, 1>,
+ def _SADDR_t16 : FLAT_Store_Pseudo<Name16, VGPROp_16, 1, 1>,
GlobalSaddrTable<1, Name16>,
True16D16Table<NAME#"_D16_HI_SADDR", NAME#"_SADDR">;
}
@@ -434,7 +434,7 @@ multiclass FLAT_Global_STORE_LDS_Pseudo<string opName> {
GlobalSaddrTable<1, opName>;
}
-class FLAT_Global_Store_AddTid_Pseudo <string opName, RegisterClass vdataClass,
+class FLAT_Global_Store_AddTid_Pseudo <string opName, RegisterOperand vdataClass,
bit EnableSaddr = 0> : FLAT_Pseudo<
opName,
(outs),
@@ -450,7 +450,7 @@ class FLAT_Global_Store_AddTid_Pseudo <string opName, RegisterClass vdataClass,
let enabled_saddr = EnableSaddr;
}
-multiclass FLAT_Global_Store_AddTid_Pseudo<string opName, RegisterClass regClass> {
+multiclass FLAT_Global_Store_AddTid_Pseudo<string opName, RegisterOperand regClass> {
def "" : FLAT_Global_Store_AddTid_Pseudo<opName, regClass>,
GlobalSaddrTable<0, opName>;
def _SADDR : FLAT_Global_Store_AddTid_Pseudo<opName, regClass, 1>,
@@ -538,14 +538,14 @@ class FlatScratchInst <string sv_op, string mode> {
string Mode = mode;
}
-class FLAT_Scratch_Load_Pseudo <string opName, RegisterClass regClass,
+class FLAT_Scratch_Load_Pseudo <string opName, RegisterOperand regClass = AVLdSt_32,
bit HasTiedOutput = 0,
bit EnableSaddr = 0,
bit EnableSVE = 0,
bit EnableVaddr = !or(EnableSVE, !not(EnableSaddr))>
: FLAT_Pseudo<
opName,
- (outs getLdStRegisterOperand<regClass>.ret:$vdst),
+ (outs regClass:$vdst),
!con(
!if(EnableSVE,
(ins VGPR_32:$vaddr, SReg_32_XEXEC_HI:$saddr, flat_offset:$offset),
@@ -554,7 +554,7 @@ class FLAT_Scratch_Load_Pseudo <string opName, RegisterClass regClass,
!if(EnableVaddr,
(ins VGPR_32:$vaddr, flat_offset:$offset),
(ins flat_offset:$offset)))),
- !if(HasTiedOutput, (ins CPol:$cpol, getLdStRegisterOperand<regClass>.ret:$vdst_in),
+ !if(HasTiedOutput, (ins CPol:$cpol, regClass:$vdst_in),
(ins CPol_0:$cpol))),
" $vdst, "#!if(EnableVaddr, "$vaddr, ", "off, ")#!if(EnableSaddr, "$saddr", "off")#"$offset$cpol"> {
let is_flat_scratch = 1;
@@ -569,10 +569,9 @@ class FLAT_Scratch_Load_Pseudo <string opName, RegisterClass regClass,
let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
}
-class FLAT_Scratch_Store_Pseudo <string opName, RegisterClass vdataClass, bit EnableSaddr = 0,
+class FLAT_Scratch_Store_Pseudo <string opName, RegisterOperand vdata_op, bit EnableSaddr = 0,
bit EnableSVE = 0,
- bit EnableVaddr = !or(EnableSVE, !not(EnableSaddr)),
- RegisterOperand vdata_op = getLdStRegisterOperand<vdataClass>.ret> : FLAT_Pseudo<
+ bit EnableVaddr = !or(EnableSVE, !not(EnableSaddr))> : FLAT_Pseudo<
opName,
(outs),
!if(EnableSVE,
@@ -594,7 +593,8 @@ class FLAT_Scratch_Store_Pseudo <string opName, RegisterClass vdataClass, bit En
let sve = EnableVaddr;
}
-multiclass FLAT_Scratch_Load_Pseudo<string opName, RegisterClass regClass, bit HasTiedOutput = 0> {
+multiclass FLAT_Scratch_Load_Pseudo<string opName, RegisterOperand regClass = AVLdSt_32,
+ bit HasTiedOutput = 0> {
def "" : FLAT_Scratch_Load_Pseudo<opName, regClass, HasTiedOutput>,
FlatScratchInst<opName, "SV">;
def _SADDR : FLAT_Scratch_Load_Pseudo<opName, regClass, HasTiedOutput, 1>,
@@ -610,29 +610,29 @@ multiclass FLAT_Scratch_Load_Pseudo<string opName, RegisterClass regClass, bit H
}
multiclass FLAT_Scratch_Load_Pseudo_t16<string opName> {
- defm "" : FLAT_Scratch_Load_Pseudo<opName, VGPR_32, 1>;
+ defm "" : FLAT_Scratch_Load_Pseudo<opName, AVLdSt_32, 1>;
defvar Name16 = opName#"_t16";
let OtherPredicates = [HasTrue16BitInsts], is_flat_scratch = 1 in {
- def _t16 : FLAT_Scratch_Load_Pseudo<Name16, VGPR_16, 0>,
+ def _t16 : FLAT_Scratch_Load_Pseudo<Name16, VGPROp_16, 0>,
FlatScratchInst<Name16, "SV">,
True16D16Table<NAME#"_HI", NAME>;
- def _SADDR_t16 : FLAT_Scratch_Load_Pseudo<Name16, VGPR_16, 0, 1>,
+ def _SADDR_t16 : FLAT_Scratch_Load_Pseudo<Name16, VGPROp_16, 0, 1>,
FlatScratchInst<Name16, "SS">,
True16D16Table<NAME#"_HI_SADDR", NAME#"_SADDR">;
let SubtargetPredicate = HasFlatScratchSVSMode in
- def _SVS_t16 : FLAT_Scratch_Load_Pseudo<Name16, VGPR_16, 0, 1, 1>,
+ def _SVS_t16 : FLAT_Scratch_Load_Pseudo<Name16, VGPROp_16, 0, 1, 1>,
FlatScratchInst<Name16, "SVS">,
True16D16Table<NAME#"_HI_SVS", NAME#"_SVS">;
let SubtargetPredicate = HasFlatScratchSTMode in
- def _ST_t16 : FLAT_Scratch_Load_Pseudo<Name16, VGPR_16, 0, 0, 0, 0>,
+ def _ST_t16 : FLAT_Scratch_Load_Pseudo<Name16, VGPROp_16, 0, 0, 0, 0>,
FlatScratchInst<Name16, "ST">,
True16D16Table<NAME#"_HI_ST", NAME#"_ST">;
}
}
-multiclass FLAT_Scratch_Store_Pseudo<string opName, RegisterClass regClass> {
+multiclass FLAT_Scratch_Store_Pseudo<string opName, RegisterOperand regClass = AVLdSt_32> {
def "" : FLAT_Scratch_Store_Pseudo<opName, regClass>,
FlatScratchInst<opName, "SV">;
def _SADDR : FLAT_Scratch_Store_Pseudo<opName, regClass, 1>,
@@ -648,24 +648,24 @@ multiclass FLAT_Scratch_Store_Pseudo<string opName, RegisterClass regClass> {
}
multiclass FLAT_Scratch_Store_Pseudo_t16<string opName> {
- defm "" : FLAT_Scratch_Store_Pseudo<opName, VGPR_32>;
+ defm "" : FLAT_Scratch_Store_Pseudo<opName, AVLdSt_32>;
defvar Name16 = opName#"_t16";
let OtherPredicates = [HasTrue16BitInsts], is_flat_scratch = 1 in {
- def _t16 : FLAT_Scratch_Store_Pseudo<Name16, VGPR_16>,
+ def _t16 : FLAT_Scratch_Store_Pseudo<Name16, VGPROp_16>,
FlatScratchInst<Name16, "SV">,
True16D16Table<NAME#"_D16_HI", NAME>;
- def _SADDR_t16 : FLAT_Scratch_Store_Pseudo<Name16, VGPR_16, 1>,
+ def _SADDR_t16 : FLAT_Scratch_Store_Pseudo<Name16, VGPROp_16, 1>,
FlatScratchInst<Name16, "SS">,
True16D16Table<NAME#"_D16_HI_SADDR", NAME#"_SADDR">;
let SubtargetPredicate = HasFlatScratchSVSMode in
- def _SVS_t16 : FLAT_Scratch_Store_Pseudo<Name16, VGPR_16, 1, 1>,
+ def _SVS_t16 : FLAT_Scratch_Store_Pseudo<Name16, VGPROp_16, 1, 1>,
FlatScratchInst<Name16, "SVS">,
True16D16Table<NAME#"_D16_HI_SVS", NAME#"_SVS">;
let SubtargetPredicate = HasFlatScratchSTMode in
- def _ST_t16 : FLAT_Scratch_Store_Pseudo<Name16, VGPR_16, 0, 0, 0>,
+ def _ST_t16 : FLAT_Scratch_Store_Pseudo<Name16, VGPROp_16, 0, 0, 0>,
FlatScratchInst<Name16, "ST">,
True16D16Table<NAME#"_D16_HI_ST", NAME#"_ST">;
}
@@ -739,11 +739,10 @@ class FLAT_AtomicRet_Pseudo<string opName, dag outs, dag ins,
multiclass FLAT_Atomic_Pseudo_NO_RTN<
string opName,
- RegisterClass vdst_rc,
+ RegisterOperand vdst_op,
ValueType vt,
ValueType data_vt = vt,
- RegisterClass data_rc = vdst_rc,
- RegisterOperand data_op = getLdStRegisterOperand<data_rc>.ret> {
+ RegisterOperand data_op = vdst_op> {
def "" : FLAT_AtomicNoRet_Pseudo <opName,
(outs),
(ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_0:$cpol),
@@ -768,12 +767,10 @@ multiclass FLAT_Atomic_Pseudo_NO_RTN<
multiclass FLAT_Atomic_Pseudo_RTN<
string opName,
- RegisterClass vdst_rc,
+ RegisterOperand vdst_op,
ValueType vt,
ValueType data_vt = vt,
- RegisterClass data_rc = vdst_rc,
- RegisterOperand data_op = getLdStRegisterOperand<data_rc>.ret,
- RegisterOperand vdst_op = getLdStRegisterOperand<vdst_rc>.ret> {
+ RegisterOperand data_op = vdst_op> {
def _RTN : FLAT_AtomicRet_Pseudo <opName,
(outs vdst_op:$vdst),
(ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_GLC1:$cpol),
@@ -799,22 +796,20 @@ multiclass FLAT_Atomic_Pseudo_RTN<
multiclass FLAT_Atomic_Pseudo<
string opName,
- RegisterClass vdst_rc,
+ RegisterOperand vdst_op,
ValueType vt,
ValueType data_vt = vt,
- RegisterClass data_rc = vdst_rc,
- RegisterOperand data_op = getLdStRegisterOperand<data_rc>.ret> {
- defm "" : FLAT_Atomic_Pseudo_NO_RTN<opName, vdst_rc, vt, data_vt, data_rc, data_op>;
- defm "" : FLAT_Atomic_Pseudo_RTN<opName, vdst_rc, vt, data_vt, data_rc, data_op>;
+ RegisterOperand data_op = vdst_op> {
+ defm "" : FLAT_Atomic_Pseudo_NO_RTN<opName, vdst_op, vt, data_vt, data_op>;
+ defm "" : FLAT_Atomic_Pseudo_RTN<opName, vdst_op, vt, data_vt, data_op>;
}
multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
string opName,
- RegisterClass vdst_rc,
+ RegisterOperand vdst_op,
ValueType vt,
ValueType data_vt = vt,
- RegisterClass data_rc = vdst_rc,
- RegisterOperand data_op = getLdStRegisterOperand<data_rc>.ret> {
+ RegisterOperand data_op = vdst_op> {
let is_flat_global = 1 in {
def "" : FLAT_AtomicNoRet_Pseudo <opName,
@@ -840,12 +835,10 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
multiclass FLAT_Global_Atomic_Pseudo_RTN<
string opName,
- RegisterClass vdst_rc,
+ RegisterOperand vdst_op,
ValueType vt,
ValueType data_vt = vt,
- RegisterClass data_rc = vdst_rc,
- RegisterOperand data_op = getLdStRegisterOperand<data_rc>.ret,
- RegisterOperand vdst_op = getLdStRegisterOperand<vdst_rc>.ret> {
+ RegisterOperand data_op = vdst_op> {
let is_flat_global = 1 in {
def _RTN : FLAT_AtomicRet_Pseudo <opName,
@@ -871,10 +864,10 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
multiclass FLAT_Global_Atomic_Pseudo<
string opName,
- RegisterClass vdst_rc,
+ RegisterOperand vdst_rc,
ValueType vt,
ValueType data_vt = vt,
- RegisterClass data_rc = vdst_rc> {
+ RegisterOperand data_rc = vdst_rc> {
defm "" : FLAT_Global_Atomic_Pseudo_NO_RTN<opName, vdst_rc, vt, data_vt, data_rc>;
defm "" : FLAT_Global_Atomic_Pseudo_RTN<opName, vdst_rc, vt, data_vt, data_rc>;
}
@@ -883,119 +876,119 @@ multiclass FLAT_Global_Atomic_Pseudo<
// Flat Instructions
//===----------------------------------------------------------------------===//
-defm FLAT_LOAD_UBYTE : FLAT_Flat_Load_Pseudo <"flat_load_ubyte", VGPR_32>;
-defm FLAT_LOAD_SBYTE : FLAT_Flat_Load_Pseudo <"flat_load_sbyte", VGPR_32>;
-defm FLAT_LOAD_USHORT : FLAT_Flat_Load_Pseudo <"flat_load_ushort", VGPR_32>;
-defm FLAT_LOAD_SSHORT : FLAT_Flat_Load_Pseudo <"flat_load_sshort", VGPR_32>;
-defm FLAT_LOAD_DWORD : FLAT_Flat_Load_Pseudo <"flat_load_dword", VGPR_32>;
-defm FLAT_LOAD_DWORDX2 : FLAT_Flat_Load_Pseudo <"flat_load_dwordx2", VReg_64>;
-defm FLAT_LOAD_DWORDX4 : FLAT_Flat_Load_Pseudo <"flat_load_dwordx4", VReg_128>;
-defm FLAT_LOAD_DWORDX3 : FLAT_Flat_Load_Pseudo <"flat_load_dwordx3", VReg_96>;
+defm FLAT_LOAD_UBYTE : FLAT_Flat_Load_Pseudo <"flat_load_ubyte">;
+defm FLAT_LOAD_SBYTE : FLAT_Flat_Load_Pseudo <"flat_load_sbyte">;
+defm FLAT_LOAD_USHORT : FLAT_Flat_Load_Pseudo <"flat_load_ushort">;
+defm FLAT_LOAD_SSHORT : FLAT_Flat_Load_Pseudo <"flat_load_sshort">;
+defm FLAT_LOAD_DWORD : FLAT_Flat_Load_Pseudo <"flat_load_dword">;
+defm FLAT_LOAD_DWORDX2 : FLAT_Flat_Load_Pseudo <"flat_load_dwordx2", AVLdSt_64>;
+defm FLAT_LOAD_DWORDX4 : FLAT_Flat_Load_Pseudo <"flat_load_dwordx4", AVLdSt_128>;
+defm FLAT_LOAD_DWORDX3 : FLAT_Flat_Load_Pseudo <"flat_load_dwordx3", AVLdSt_96>;
-defm FLAT_STORE_DWORD : FLAT_Flat_Store_Pseudo <"flat_store_dword", VGPR_32>;
-defm FLAT_STORE_DWORDX2 : FLAT_Flat_Store_Pseudo <"flat_store_dwordx2", VReg_64>;
-defm FLAT_STORE_DWORDX4 : FLAT_Flat_Store_Pseudo <"flat_store_dwordx4", VReg_128>;
-defm FLAT_STORE_DWORDX3 : FLAT_Flat_Store_Pseudo <"flat_store_dwordx3", VReg_96>;
+defm FLAT_STORE_DWORD : FLAT_Flat_Store_Pseudo <"flat_store_dword">;
+defm FLAT_STORE_DWORDX2 : FLAT_Flat_Store_Pseudo <"flat_store_dwordx2", AVLdSt_64>;
+defm FLAT_STORE_DWORDX4 : FLAT_Flat_Store_Pseudo <"flat_store_dwordx4", AVLdSt_128>;
+defm FLAT_STORE_DWORDX3 : FLAT_Flat_Store_Pseudo <"flat_store_dwordx3", AVLdSt_96>;
let SubtargetPredicate = HasD16LoadStore in {
let TiedSourceNotRead = 1 in {
-defm FLAT_LOAD_UBYTE_D16_HI : FLAT_Flat_Load_Pseudo <"flat_load_ubyte_d16_hi", VGPR_32, 1>;
+defm FLAT_LOAD_UBYTE_D16_HI : FLAT_Flat_Load_Pseudo <"flat_load_ubyte_d16_hi", AVLdSt_32, 1>;
defm FLAT_LOAD_UBYTE_D16 : FLAT_Flat_Load_Pseudo_t16 <"flat_load_ubyte_d16">;
-defm FLAT_LOAD_SBYTE_D16_HI : FLAT_Flat_Load_Pseudo <"flat_load_sbyte_d16_hi", VGPR_32, 1>;
+defm FLAT_LOAD_SBYTE_D16_HI : FLAT_Flat_Load_Pseudo <"flat_load_sbyte_d16_hi", AVLdSt_32, 1>;
defm FLAT_LOAD_SBYTE_D16 : FLAT_Flat_Load_Pseudo_t16 <"flat_load_sbyte_d16">;
-defm FLAT_LOAD_SHORT_D16_HI : FLAT_Flat_Load_Pseudo <"flat_load_short_d16_hi", VGPR_32, 1>;
+defm FLAT_LOAD_SHORT_D16_HI : FLAT_Flat_Load_Pseudo <"flat_load_short_d16_hi", AVLdSt_32, 1>;
defm FLAT_LOAD_SHORT_D16 : FLAT_Flat_Load_Pseudo_t16 <"flat_load_short_d16">;
}
-defm FLAT_STORE_BYTE_D16_HI : FLAT_Flat_Store_Pseudo <"flat_store_byte_d16_hi", VGPR_32>;
-defm FLAT_STORE_SHORT_D16_HI : FLAT_Flat_Store_Pseudo <"flat_store_short_d16_hi", VGPR_32>;
+defm FLAT_STORE_BYTE_D16_HI : FLAT_Flat_Store_Pseudo <"flat_store_byte_d16_hi">;
+defm FLAT_STORE_SHORT_D16_HI : FLAT_Flat_Store_Pseudo <"flat_store_short_d16_hi">;
}
defm FLAT_STORE_BYTE : FLAT_Flat_Store_Pseudo_t16 <"flat_store_byte">;
defm FLAT_STORE_SHORT : FLAT_Flat_Store_Pseudo_t16 <"flat_store_short">;
defm FLAT_ATOMIC_CMPSWAP : FLAT_Atomic_Pseudo <"flat_atomic_cmpswap",
- VGPR_32, i32, v2i32, VReg_64>;
+ AVLdSt_32, i32, v2i32, AVLdSt_64>;
defm FLAT_ATOMIC_CMPSWAP_X2 ...
[truncated]
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rampitec
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September 4, 2025 05:14
This will make it easier to precisely express operand constraints without having the implicit getLdStRegisterOperand at the bottom. Also prunes out using AV classes in some instructions where AGPRs are not relevant.
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This will make it easier to precisely express operand constraints
without having the implicit getLdStRegisterOperand at the bottom.
Also prunes out using AV classes in some instructions where AGPRs
are not relevant.