release/21.x: [Hexagon] Add missing operand when disassembling Y4_crswap10 (#153849) #153926
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…3849) Auto-generated decoder fails to add the $sgp10 operand because it has no encoding bits. Work around this by adding the missing operand after decoding is complete. Fixes llvm#153829. (cherry picked from commit 76d993b)
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@quic-akaryaki What do you think about merging this PR to the release branch? |
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@llvm/pr-subscribers-mc Author: None (llvmbot) ChangesBackport 76d993b Requested by: @androm3da Full diff: https://github.com/llvm/llvm-project/pull/153926.diff 2 Files Affected:
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
index 22cff7c80fa01..bcddb540d35dc 100644
--- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
+++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -526,6 +526,9 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
MI.insert(MI.begin() + 1,
MCOperand::createExpr(MCConstantExpr::create(-1, getContext())));
break;
+ case Hexagon::Y4_crswap10:
+ MI.addOperand(MCOperand::createReg(Hexagon::SGP1_0));
+ break;
default:
break;
}
diff --git a/llvm/test/MC/Hexagon/system-inst.s b/llvm/test/MC/Hexagon/system-inst.s
index 7bc1533598532..07f7ca0acb2dc 100644
--- a/llvm/test/MC/Hexagon/system-inst.s
+++ b/llvm/test/MC/Hexagon/system-inst.s
@@ -89,6 +89,9 @@ crswap(r12,sgp0)
#CHECK: 652dc000 { crswap(r13,sgp1) }
crswap(r13,sgp1)
+#CHECK: 6d8ec000 { crswap(r15:14,s1:0) }
+crswap(r15:14,sgp1:0)
+
#CHECK: 660fc00e { r14 = getimask(r15) }
r14=getimask(r15)
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@llvm/pr-subscribers-backend-hexagon Author: None (llvmbot) ChangesBackport 76d993b Requested by: @androm3da Full diff: https://github.com/llvm/llvm-project/pull/153926.diff 2 Files Affected:
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
index 22cff7c80fa01..bcddb540d35dc 100644
--- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
+++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -526,6 +526,9 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
MI.insert(MI.begin() + 1,
MCOperand::createExpr(MCConstantExpr::create(-1, getContext())));
break;
+ case Hexagon::Y4_crswap10:
+ MI.addOperand(MCOperand::createReg(Hexagon::SGP1_0));
+ break;
default:
break;
}
diff --git a/llvm/test/MC/Hexagon/system-inst.s b/llvm/test/MC/Hexagon/system-inst.s
index 7bc1533598532..07f7ca0acb2dc 100644
--- a/llvm/test/MC/Hexagon/system-inst.s
+++ b/llvm/test/MC/Hexagon/system-inst.s
@@ -89,6 +89,9 @@ crswap(r12,sgp0)
#CHECK: 652dc000 { crswap(r13,sgp1) }
crswap(r13,sgp1)
+#CHECK: 6d8ec000 { crswap(r15:14,s1:0) }
+crswap(r15:14,sgp1:0)
+
#CHECK: 660fc00e { r14 = getimask(r15) }
r14=getimask(r15)
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ping @quic-akaryaki for review. |
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moved this from Needs Review
to Needs Merge
in LLVM Release Status
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Backport 76d993b
Requested by: @androm3da