Skip to content

[AArch64] Ensure we transferImpOps on BSP pseudo expansions. #149456

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jul 22, 2025
Merged

[AArch64] Ensure we transferImpOps on BSP pseudo expansions. #149456

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
66 changes: 36 additions & 30 deletions llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1205,32 +1205,36 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
Register DstReg = MI.getOperand(0).getReg();
if (DstReg == MI.getOperand(3).getReg()) {
// Expand to BIT
BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BITv8i8
: AArch64::BITv16i8))
.add(MI.getOperand(0))
.add(MI.getOperand(3))
.add(MI.getOperand(2))
.add(MI.getOperand(1));
auto I = BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BITv8i8
: AArch64::BITv16i8))
.add(MI.getOperand(0))
.add(MI.getOperand(3))
.add(MI.getOperand(2))
.add(MI.getOperand(1));
transferImpOps(MI, I, I);
Copy link
Contributor

@rj-jesus rj-jesus Jul 18, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Nit: would it be worth declaring MachineInstrBuilder MIB before the if-else chain and moving transferImpOps(MI, MIB, MIB); just before MI.eraseFromParent?

} else if (DstReg == MI.getOperand(2).getReg()) {
// Expand to BIF
BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BIFv8i8
: AArch64::BIFv16i8))
.add(MI.getOperand(0))
.add(MI.getOperand(2))
.add(MI.getOperand(3))
.add(MI.getOperand(1));
auto I = BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BIFv8i8
: AArch64::BIFv16i8))
.add(MI.getOperand(0))
.add(MI.getOperand(2))
.add(MI.getOperand(3))
.add(MI.getOperand(1));
transferImpOps(MI, I, I);
} else {
// Expand to BSL, use additional move if required
if (DstReg == MI.getOperand(1).getReg()) {
BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BSLv8i8
: AArch64::BSLv16i8))
.add(MI.getOperand(0))
.add(MI.getOperand(1))
.add(MI.getOperand(2))
.add(MI.getOperand(3));
auto I =
BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BSLv8i8
: AArch64::BSLv16i8))
.add(MI.getOperand(0))
.add(MI.getOperand(1))
.add(MI.getOperand(2))
.add(MI.getOperand(3));
transferImpOps(MI, I, I);
} else {
BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::ORRv8i8
Expand All @@ -1240,15 +1244,17 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
getRenamableRegState(MI.getOperand(0).isRenamable()))
.add(MI.getOperand(1))
.add(MI.getOperand(1));
BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BSLv8i8
: AArch64::BSLv16i8))
.add(MI.getOperand(0))
.addReg(DstReg,
RegState::Kill |
getRenamableRegState(MI.getOperand(0).isRenamable()))
.add(MI.getOperand(2))
.add(MI.getOperand(3));
auto I2 =
BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BSLv8i8
: AArch64::BSLv16i8))
.add(MI.getOperand(0))
.addReg(DstReg,
RegState::Kill | getRenamableRegState(
MI.getOperand(0).isRenamable()))
.add(MI.getOperand(2))
.add(MI.getOperand(3));
transferImpOps(MI, I2, I2);
}
}
MI.eraseFromParent();
Expand Down
98 changes: 98 additions & 0 deletions llvm/test/CodeGen/AArch64/bsp_implicit_ops.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,98 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass aarch64-expand-pseudo -verify-machineinstrs %s -o - | FileCheck %s


---
name: BSL_COPY
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7


; CHECK-LABEL: name: BSL_COPY
; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $q2 = ORRv16i8 killed renamable $q20, killed renamable $q20
; CHECK-NEXT: renamable $q2 = BSLv16i8 killed renamable $q2, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
; CHECK-NEXT: $q24 = ORRv16i8 $q2, killed $q2
; CHECK-NEXT: $q25 = ORRv16i8 $q3, killed $q3
; CHECK-NEXT: RET undef $lr, implicit $q22
renamable $q2 = BSPv16i8 killed renamable $q20, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
$q22 = ORRv16i8 $q0, killed $q0
$q23 = ORRv16i8 $q1, killed $q1
$q24 = ORRv16i8 $q2, killed $q2
$q25 = ORRv16i8 $q3, killed $q3
RET_ReallyLR implicit $q22
...
---
name: BSL
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7

; CHECK-LABEL: name: BSL
; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $q2 = BSLv16i8 killed renamable $q2, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
; CHECK-NEXT: $q24 = ORRv16i8 $q2, killed $q2
; CHECK-NEXT: $q25 = ORRv16i8 $q3, killed $q3
; CHECK-NEXT: RET undef $lr, implicit $q22
renamable $q2 = BSPv16i8 killed renamable $q2, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
$q22 = ORRv16i8 $q0, killed $q0
$q23 = ORRv16i8 $q1, killed $q1
$q24 = ORRv16i8 $q2, killed $q2
$q25 = ORRv16i8 $q3, killed $q3
RET_ReallyLR implicit $q22
...
---
name: BIF
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7

; CHECK-LABEL: name: BIF
; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $q2 = BIFv16i8 renamable $q2, renamable $q6, killed renamable $q20, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
; CHECK-NEXT: $q24 = ORRv16i8 $q2, killed $q2
; CHECK-NEXT: $q25 = ORRv16i8 $q3, killed $q3
; CHECK-NEXT: RET undef $lr, implicit $q22
renamable $q2 = BSPv16i8 killed renamable $q20, renamable $q2, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
$q22 = ORRv16i8 $q0, killed $q0
$q23 = ORRv16i8 $q1, killed $q1
$q24 = ORRv16i8 $q2, killed $q2
$q25 = ORRv16i8 $q3, killed $q3
RET_ReallyLR implicit $q22
...
---
name: BIT
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7

; CHECK-LABEL: name: BIT
; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $q2 = BITv16i8 renamable $q2, renamable $q21, killed renamable $q20, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
; CHECK-NEXT: $q24 = ORRv16i8 $q2, killed $q2
; CHECK-NEXT: $q25 = ORRv16i8 $q3, killed $q3
; CHECK-NEXT: RET undef $lr, implicit $q22
renamable $q2 = BSPv16i8 killed renamable $q20, renamable $q21, renamable $q2, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
$q22 = ORRv16i8 $q0, killed $q0
$q23 = ORRv16i8 $q1, killed $q1
$q24 = ORRv16i8 $q2, killed $q2
$q25 = ORRv16i8 $q3, killed $q3
RET_ReallyLR implicit $q22
...
Loading