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[flang] update ppc lit tests after using vector.insert and vector.extract (NFC) #148775

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Jul 18, 2025
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[flang] update ppc lit tests after using vector.insert and vector.extract (NFC) #148775

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5 changes: 3 additions & 2 deletions flang/test/Lower/PowerPC/ppc-vec-extract-elem-order.f90
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
! RUN: %flang_fc1 -flang-experimental-hlfir -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="LLVMIR" %s
! RUN: %flang_fc1 -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="LLVMIR" %s
! REQUIRES: target=powerpc{{.*}}

!CHECK-LABEL: vec_extract_testr4i8
Expand Down Expand Up @@ -27,6 +27,7 @@ subroutine vec_extract_testi8i1(arg1, arg2, r)
! LLVMIR: %[[arg2:.*]] = load i8, ptr %{{[0-9]}}, align 1
! LLVMIR: %[[urem:.*]] = urem i8 %[[arg2]], 2
! LLVMIR: %[[sub:.*]] = sub i8 1, %[[urem]]
! LLVMIR: %[[r:.*]] = extractelement <2 x i64> %[[arg1]], i8 %[[sub]]
! LLVMIR: %[[idx:.*]] = zext i8 %[[sub]] to i64
! LLVMIR: %[[r:.*]] = extractelement <2 x i64> %[[arg1]], i64 %[[idx]]
! LLVMIR: store i64 %[[r]], ptr %{{[0-9]}}, align 8
end subroutine vec_extract_testi8i1
142 changes: 80 additions & 62 deletions flang/test/Lower/PowerPC/ppc-vec-extract.f90
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-LE" %s
! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-BE" %s
! RUN: %flang_fc1 -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-LE" %s
! RUN: %flang_fc1 -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-BE" %s
! REQUIRES: target=powerpc{{.*}}

!-------------
Expand All @@ -19,8 +19,9 @@ subroutine vec_extract_testf32(x, i1, i2, i4, i8)
! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 4
! LLVMIR-BE: %[[s:.*]] = sub i8 3, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <4 x float> %[[x]], i8 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <4 x float> %[[x]], i8 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i8 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i8 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <4 x float> %[[x]], i64 %[[idx]]
! LLVMIR: store float %[[r]], ptr %{{[0-9]}}, align 4

r = vec_extract(x, i2)
Expand All @@ -29,8 +30,9 @@ subroutine vec_extract_testf32(x, i1, i2, i4, i8)
! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 4
! LLVMIR-BE: %[[s:.*]] = sub i16 3, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <4 x float> %[[x]], i16 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <4 x float> %[[x]], i16 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i16 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i16 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <4 x float> %[[x]], i64 %[[idx]]
! LLVMIR: store float %[[r]], ptr %{{[0-9]}}, align 4

r = vec_extract(x, i4)
Expand All @@ -39,18 +41,19 @@ subroutine vec_extract_testf32(x, i1, i2, i4, i8)
! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 4
! LLVMIR-BE: %[[s:.*]] = sub i32 3, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <4 x float> %[[x]], i32 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <4 x float> %[[x]], i32 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i32 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i32 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <4 x float> %[[x]], i64 %[[idx]]
! LLVMIR: store float %[[r]], ptr %{{[0-9]}}, align 4

r = vec_extract(x, i8)

! LLVMIR: %[[x:.*]] = load <4 x float>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 4
! LLVMIR-BE: %[[s:.*]] = sub i64 3, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <4 x float> %[[x]], i64 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <4 x float> %[[x]], i64 %[[s]]
! LLVMIR-BE: %[[u:.*]] = urem i64 %[[i8]], 4
! LLVMIR-BE: %[[idx:.*]] = sub i64 3, %[[u]]
! LLVMIR-LE: %[[idx:.*]] = urem i64 %[[i8]], 4
! LLVMIR: %[[r:.*]] = extractelement <4 x float> %[[x]], i64 %[[idx]]
! LLVMIR: store float %[[r]], ptr %{{[0-9]}}, align 4
end subroutine vec_extract_testf32

Expand All @@ -68,8 +71,9 @@ subroutine vec_extract_testf64(x, i1, i2, i4, i8)
! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 2
! LLVMIR-BE: %[[s:.*]] = sub i8 1, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <2 x double> %[[x]], i8 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <2 x double> %[[x]], i8 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i8 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i8 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <2 x double> %[[x]], i64 %[[idx]]
! LLVMIR: store double %[[r]], ptr %{{[0-9]}}, align 8

r = vec_extract(x, i2)
Expand All @@ -78,8 +82,9 @@ subroutine vec_extract_testf64(x, i1, i2, i4, i8)
! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 2
! LLVMIR-BE: %[[s:.*]] = sub i16 1, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <2 x double> %[[x]], i16 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <2 x double> %[[x]], i16 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i16 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i16 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <2 x double> %[[x]], i64 %[[idx]]
! LLVMIR: store double %[[r]], ptr %{{[0-9]}}, align 8


Expand All @@ -89,18 +94,19 @@ subroutine vec_extract_testf64(x, i1, i2, i4, i8)
! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 2
! LLVMIR-BE: %[[s:.*]] = sub i32 1, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <2 x double> %[[x]], i32 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <2 x double> %[[x]], i32 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i32 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i32 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <2 x double> %[[x]], i64 %[[idx]]
! LLVMIR: store double %[[r]], ptr %{{[0-9]}}, align 8

r = vec_extract(x, i8)

! LLVMIR: %[[x:.*]] = load <2 x double>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 2
! LLVMIR-BE: %[[s:.*]] = sub i64 1, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <2 x double> %[[x]], i64 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <2 x double> %[[x]], i64 %[[s]]
! LLVMIR-BE: %[[u:.*]] = urem i64 %[[i8]], 2
! LLVMIR-BE: %[[idx:.*]] = sub i64 1, %[[u]]
! LLVMIR-LE: %[[idx:.*]] = urem i64 %[[i8]], 2
! LLVMIR: %[[r:.*]] = extractelement <2 x double> %[[x]], i64 %[[idx]]
! LLVMIR: store double %[[r]], ptr %{{[0-9]}}, align 8
end subroutine vec_extract_testf64

Expand All @@ -118,8 +124,9 @@ subroutine vec_extract_testi8(x, i1, i2, i4, i8)
! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 16
! LLVMIR-BE: %[[s:.*]] = sub i8 15, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i8 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i8 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i8 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i8 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <16 x i8> %[[x]], i64 %[[idx]]
! LLVMIR: store i8 %[[r]], ptr %{{[0-9]}}, align 1

r = vec_extract(x, i2)
Expand All @@ -128,8 +135,9 @@ subroutine vec_extract_testi8(x, i1, i2, i4, i8)
! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 16
! LLVMIR-BE: %[[s:.*]] = sub i16 15, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i16 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i16 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i16 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i16 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <16 x i8> %[[x]], i64 %[[idx]]
! LLVMIR: store i8 %[[r]], ptr %{{[0-9]}}, align 1

r = vec_extract(x, i4)
Expand All @@ -138,18 +146,19 @@ subroutine vec_extract_testi8(x, i1, i2, i4, i8)
! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 16
! LLVMIR-BE: %[[s:.*]] = sub i32 15, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i32 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i32 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i32 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i32 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <16 x i8> %[[x]], i64 %[[idx]]
! LLVMIR: store i8 %[[r]], ptr %{{[0-9]}}, align 1

r = vec_extract(x, i8)

! LLVMIR: %[[x:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 16
! LLVMIR-BE: %[[s:.*]] = sub i64 15, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i64 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i64 %[[s]]
! LLVMIR-BE: %[[u:.*]] = urem i64 %[[i8]], 16
! LLVMIR-BE: %[[idx:.*]] = sub i64 15, %[[u]]
! LLVMIR-LE: %[[idx:.*]] = urem i64 %[[i8]], 16
! LLVMIR: %[[r:.*]] = extractelement <16 x i8> %[[x]], i64 %[[idx]]
! LLVMIR: store i8 %[[r]], ptr %{{[0-9]}}, align 1
end subroutine vec_extract_testi8

Expand All @@ -167,8 +176,9 @@ subroutine vec_extract_testi16(x, i1, i2, i4, i8)
! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 8
! LLVMIR-BE: %[[s:.*]] = sub i8 7, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i8 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i8 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i8 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i8 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <8 x i16> %[[x]], i64 %[[idx]]
! LLVMIR: store i16 %[[r]], ptr %{{[0-9]}}, align 2

r = vec_extract(x, i2)
Expand All @@ -177,8 +187,9 @@ subroutine vec_extract_testi16(x, i1, i2, i4, i8)
! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 8
! LLVMIR-BE: %[[s:.*]] = sub i16 7, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i16 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i16 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i16 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i16 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <8 x i16> %[[x]], i64 %[[idx]]
! LLVMIR: store i16 %[[r]], ptr %{{[0-9]}}, align 2

r = vec_extract(x, i4)
Expand All @@ -187,18 +198,19 @@ subroutine vec_extract_testi16(x, i1, i2, i4, i8)
! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 8
! LLVMIR-BE: %[[s:.*]] = sub i32 7, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i32 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i32 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i32 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i32 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <8 x i16> %[[x]], i64 %[[idx]]
! LLVMIR: store i16 %[[r]], ptr %{{[0-9]}}, align 2

r = vec_extract(x, i8)

! LLVMIR: %[[x:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 8
! LLVMIR-BE: %[[s:.*]] = sub i64 7, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i64 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i64 %[[s]]
! LLVMIR-BE: %[[u:.*]] = urem i64 %[[i8]], 8
! LLVMIR-BE: %[[idx:.*]] = sub i64 7, %[[u]]
! LLVMIR-LE: %[[idx:.*]] = urem i64 %[[i8]], 8
! LLVMIR: %[[r:.*]] = extractelement <8 x i16> %[[x]], i64 %[[idx]]
! LLVMIR: store i16 %[[r]], ptr %{{[0-9]}}, align 2
end subroutine vec_extract_testi16

Expand All @@ -216,8 +228,9 @@ subroutine vec_extract_testi32(x, i1, i2, i4, i8)
! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 4
! LLVMIR-BE: %[[s:.*]] = sub i8 3, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i8 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i8 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i8 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i8 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <4 x i32> %[[x]], i64 %[[idx]]
! LLVMIR: store i32 %[[r]], ptr %{{[0-9]}}, align 4

r = vec_extract(x, i2)
Expand All @@ -226,8 +239,9 @@ subroutine vec_extract_testi32(x, i1, i2, i4, i8)
! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 4
! LLVMIR-BE: %[[s:.*]] = sub i16 3, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i16 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i16 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i16 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i16 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <4 x i32> %[[x]], i64 %[[idx]]
! LLVMIR: store i32 %[[r]], ptr %{{[0-9]}}, align 4

r = vec_extract(x, i4)
Expand All @@ -236,18 +250,19 @@ subroutine vec_extract_testi32(x, i1, i2, i4, i8)
! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 4
! LLVMIR-BE: %[[s:.*]] = sub i32 3, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i32 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i32 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i32 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i32 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <4 x i32> %[[x]], i64 %[[idx]]
! LLVMIR: store i32 %[[r]], ptr %{{[0-9]}}, align 4

r = vec_extract(x, i8)

! LLVMIR: %[[x:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 4
! LLVMIR-BE: %[[s:.*]] = sub i64 3, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i64 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i64 %[[s]]
! LLVMIR-BE: %[[u:.*]] = urem i64 %[[i8]], 4
! LLVMIR-BE: %[[idx:.*]] = sub i64 3, %[[u]]
! LLVMIR-LE: %[[idx:.*]] = urem i64 %[[i8]], 4
! LLVMIR: %[[r:.*]] = extractelement <4 x i32> %[[x]], i64 %[[idx]]
! LLVMIR: store i32 %[[r]], ptr %{{[0-9]}}, align 4
end subroutine vec_extract_testi32

Expand All @@ -265,8 +280,9 @@ subroutine vec_extract_testi64(x, i1, i2, i4, i8)
! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 2
! LLVMIR-BE: %[[s:.*]] = sub i8 1, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i8 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i8 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i8 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i8 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <2 x i64> %[[x]], i64 %[[idx]]
! LLVMIR: store i64 %[[r]], ptr %{{[0-9]}}, align 8

r = vec_extract(x, i2)
Expand All @@ -275,8 +291,9 @@ subroutine vec_extract_testi64(x, i1, i2, i4, i8)
! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 2
! LLVMIR-BE: %[[s:.*]] = sub i16 1, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i16 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i16 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i16 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i16 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <2 x i64> %[[x]], i64 %[[idx]]
! LLVMIR: store i64 %[[r]], ptr %{{[0-9]}}, align 8

r = vec_extract(x, i4)
Expand All @@ -285,17 +302,18 @@ subroutine vec_extract_testi64(x, i1, i2, i4, i8)
! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 2
! LLVMIR-BE: %[[s:.*]] = sub i32 1, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i32 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i32 %[[s]]
! LLVMIR-BE: %[[idx:.*]] = zext i32 %[[s]] to i64
! LLVMIR-LE: %[[idx:.*]] = zext i32 %[[u]] to i64
! LLVMIR: %[[r:.*]] = extractelement <2 x i64> %[[x]], i64 %[[idx]]
! LLVMIR: store i64 %[[r]], ptr %{{[0-9]}}, align 8

r = vec_extract(x, i8)

! LLVMIR: %[[x:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 2
! LLVMIR-BE: %[[s:.*]] = sub i64 1, %[[u]]
! LLVMIR-LE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i64 %[[u]]
! LLVMIR-BE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i64 %[[s]]
! LLVMIR-BE: %[[u:.*]] = urem i64 %[[i8]], 2
! LLVMIR-BE: %[[idx:.*]] = sub i64 1, %[[u]]
! LLVMIR-LE: %[[idx:.*]] = urem i64 %[[i8]], 2
! LLVMIR: %[[r:.*]] = extractelement <2 x i64> %[[x]], i64 %[[idx]]
! LLVMIR: store i64 %[[r]], ptr %{{[0-9]}}, align 8
end subroutine vec_extract_testi64
5 changes: 3 additions & 2 deletions flang/test/Lower/PowerPC/ppc-vec-insert-elem-order.f90
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@@ -1,4 +1,4 @@
! RUN: %flang_fc1 -flang-experimental-hlfir -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="LLVMIR" %s
! RUN: %flang_fc1 -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="LLVMIR" %s
! REQUIRES: target=powerpc{{.*}}

!CHECK-LABEL: vec_insert_testf32i64
Expand Down Expand Up @@ -31,6 +31,7 @@ subroutine vec_insert_testi64i8(v, x, i1, i2, i4, i8)
! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
! LLVMIR: %[[urem:.*]] = urem i8 %[[i1]], 2
! LLVMIR: %[[sub:.*]] = sub i8 1, %[[urem]]
! LLVMIR: %[[r:.*]] = insertelement <2 x i64> %[[x]], i64 %[[v]], i8 %[[sub]]
! LLVMIR: %[[idx:.*]] = zext i8 %[[sub]] to i64
! LLVMIR: %[[r:.*]] = insertelement <2 x i64> %[[x]], i64 %[[v]], i64 %[[idx]]
! LLVMIR: store <2 x i64> %[[r]], ptr %{{[0-9]}}, align 16
end subroutine vec_insert_testi64i8
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