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[X86][FP16] Widen 128/256-bit CVTTP2xI to 512-bit when VLX not enabled #142763

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Merged
merged 2 commits into from
Jun 5, 2025
Merged

[X86][FP16] Widen 128/256-bit CVTTP2xI to 512-bit when VLX not enabled #142763

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ba50d21
[X86][FP16] Winden 128/256-bit CVTTP2xI to 512-bit when VLX not enabled
phoebewang Jun 4, 2025
e8ef2f1
Use widenSubVector
phoebewang Jun 5, 2025
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49 changes: 34 additions & 15 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2371,6 +2371,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::LLRINT, MVT::v8f16, Legal);
}

setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v8i16, Custom);
setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v8i16, Custom);

if (Subtarget.hasVLX()) {
setGroup(MVT::v8f16);
setGroup(MVT::v16f16);
Expand All @@ -2386,10 +2391,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Legal);
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v8i16, Legal);

setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v8i16, Custom);
setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v8i16, Custom);
setOperationAction(ISD::FP_ROUND, MVT::v8f16, Legal);
setOperationAction(ISD::STRICT_FP_ROUND, MVT::v8f16, Legal);
setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Custom);
Expand Down Expand Up @@ -20010,10 +20011,12 @@ static SDValue promoteXINT_TO_FP(SDValue Op, const SDLoc &dl,

static bool isLegalConversion(MVT VT, MVT FloatVT, bool IsSigned,
const X86Subtarget &Subtarget) {
if (VT == MVT::v4i32 && Subtarget.hasSSE2() && IsSigned)
return true;
if (VT == MVT::v8i32 && Subtarget.hasAVX() && IsSigned)
return true;
if (FloatVT.getScalarType() != MVT::f16 || Subtarget.hasVLX()) {
if (VT == MVT::v4i32 && Subtarget.hasSSE2() && IsSigned)
return true;
if (VT == MVT::v8i32 && Subtarget.hasAVX() && IsSigned)
return true;
}
if (Subtarget.hasVLX() && (VT == MVT::v4i32 || VT == MVT::v8i32))
return true;
if (Subtarget.useAVX512Regs()) {
Expand Down Expand Up @@ -21552,6 +21555,7 @@ SDValue X86TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
bool IsStrict = Op->isStrictFPOpcode();
bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT ||
Op.getOpcode() == ISD::STRICT_FP_TO_SINT;
bool HasVLX = Subtarget.hasVLX();
MVT VT = Op->getSimpleValueType(0);
SDValue Src = Op.getOperand(IsStrict ? 1 : 0);
SDValue Chain = IsStrict ? Op->getOperand(0) : SDValue();
Expand Down Expand Up @@ -21582,7 +21586,7 @@ SDValue X86TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
else
Opc = IsSigned ? X86ISD::CVTTP2SI : X86ISD::CVTTP2UI;

if (!IsSigned && !Subtarget.hasVLX()) {
if (!IsSigned && !HasVLX) {
assert(Subtarget.useAVX512Regs() && "Unexpected features!");
// Widen to 512-bits.
ResVT = MVT::v8i32;
Expand Down Expand Up @@ -21612,22 +21616,33 @@ SDValue X86TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
}

if (Subtarget.hasFP16() && SrcVT.getVectorElementType() == MVT::f16) {
if (VT == MVT::v8i16 || VT == MVT::v16i16 || VT == MVT::v32i16)
if ((HasVLX && (VT == MVT::v8i16 || VT == MVT::v16i16)) ||
VT == MVT::v32i16)
return Op;

MVT ResVT = VT;
MVT EleVT = VT.getVectorElementType();
if (EleVT != MVT::i64)
ResVT = EleVT == MVT::i32 ? MVT::v4i32 : MVT::v8i16;

if (SrcVT != MVT::v8f16) {
if (SrcVT == MVT::v2f16 || SrcVT == MVT::v4f16) {
SDValue Tmp =
IsStrict ? DAG.getConstantFP(0.0, dl, SrcVT) : DAG.getUNDEF(SrcVT);
SmallVector<SDValue, 4> Ops(SrcVT == MVT::v2f16 ? 4 : 2, Tmp);
Ops[0] = Src;
Src = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8f16, Ops);
}

if (!HasVLX) {
assert(Subtarget.useAVX512Regs() && "Unexpected features!");
// Widen to 512-bits.
unsigned IntSize = EleVT.getSizeInBits();
unsigned Num = IntSize > 16 ? 512 / IntSize : 32;
ResVT = MVT::getVectorVT(EleVT, Num);
Src = widenSubVector(MVT::getVectorVT(MVT::f16, Num), Src, IsStrict,
Subtarget, DAG, dl);
}

if (IsStrict) {
Res = DAG.getNode(IsSigned ? X86ISD::STRICT_CVTTP2SI
: X86ISD::STRICT_CVTTP2UI,
Expand All @@ -21640,7 +21655,8 @@ SDValue X86TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {

// TODO: Need to add exception check code for strict FP.
if (EleVT.getSizeInBits() < 16) {
ResVT = MVT::getVectorVT(EleVT, 8);
if (HasVLX)
ResVT = MVT::getVectorVT(EleVT, 8);
Res = DAG.getNode(ISD::TRUNCATE, dl, ResVT, Res);
}

Expand Down Expand Up @@ -34123,12 +34139,10 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
}

if (IsStrict) {
Opc = IsSigned ? X86ISD::STRICT_CVTTP2SI : X86ISD::STRICT_CVTTP2UI;
Res =
DAG.getNode(Opc, dl, {ResVT, MVT::Other}, {N->getOperand(0), Src});
Chain = Res.getValue(1);
} else {
Opc = IsSigned ? X86ISD::CVTTP2SI : X86ISD::CVTTP2UI;
Res = DAG.getNode(Opc, dl, ResVT, Src);
}

Expand Down Expand Up @@ -44126,7 +44140,12 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
// Conversions.
// TODO: Add more CVT opcodes when we have test coverage.
case X86ISD::CVTTP2SI:
case X86ISD::CVTTP2UI:
case X86ISD::CVTTP2UI: {
if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f16 &&
!Subtarget.hasVLX())
break;
[[fallthrough]];
}
case X86ISD::CVTPH2PS: {
SDLoc DL(Op);
unsigned Scale = SizeInBits / ExtSizeInBits;
Expand Down
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