Skip to content

[AArch64][GlobalISel] Ensure we have a insert-subreg v4i32 GPR pattern #142724

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jun 6, 2025
Merged

[AArch64][GlobalISel] Ensure we have a insert-subreg v4i32 GPR pattern #142724

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
17 changes: 7 additions & 10 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7269,6 +7269,13 @@ def : Pat<(v4i16 (vec_ins_or_scal_vec GPR32:$Rn)),
(SUBREG_TO_REG (i32 0),
(f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;

def : Pat<(v2i32 (vec_ins_or_scal_vec GPR32:$Rn)),
(INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), GPR32:$Rn, ssub)>;
def : Pat<(v4i32 (vec_ins_or_scal_vec GPR32:$Rn)),
(INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GPR32:$Rn, ssub)>;
def : Pat<(v2i64 (vec_ins_or_scal_vec GPR64:$Rn)),
(INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GPR64:$Rn, dsub)>;

def : Pat<(v4f16 (vec_ins_or_scal_vec (f16 FPR16:$Rn))),
(INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
def : Pat<(v8f16 (vec_ins_or_scal_vec (f16 FPR16:$Rn))),
Expand All @@ -7279,16 +7286,6 @@ def : Pat<(v4bf16 (vec_ins_or_scal_vec (bf16 FPR16:$Rn))),
def : Pat<(v8bf16 (vec_ins_or_scal_vec (bf16 FPR16:$Rn))),
(INSERT_SUBREG (v8bf16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;

def : Pat<(v2i32 (vec_ins_or_scal_vec (i32 FPR32:$Rn))),
(v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
(i32 FPR32:$Rn), ssub))>;
def : Pat<(v4i32 (vec_ins_or_scal_vec (i32 FPR32:$Rn))),
(v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
(i32 FPR32:$Rn), ssub))>;
def : Pat<(v2i64 (vec_ins_or_scal_vec (i64 FPR64:$Rn))),
(v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
(i64 FPR64:$Rn), dsub))>;

def : Pat<(v4f16 (vec_ins_or_scal_vec (f16 FPR16:$Rn))),
(INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
def : Pat<(v8f16 (vec_ins_or_scal_vec (f16 FPR16:$Rn))),
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector-widen-crash.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ define i32 @bar() {
; CHECK-NEXT: movi.2d v0, #0000000000000000
; CHECK-NEXT: umov.b w8, v0[0]
; CHECK-NEXT: umov.b w9, v0[1]
; CHECK-NEXT: mov.s v1[0], w8
; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: umov.b w8, v0[2]
; CHECK-NEXT: mov.s v1[1], w9
; CHECK-NEXT: umov.b w9, v0[3]
Expand Down
11 changes: 4 additions & 7 deletions llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-build-vector-to-dup.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -57,15 +57,12 @@ body: |
; SELECT-NEXT: %r:gpr32 = COPY $w0
; SELECT-NEXT: %q:gpr32 = COPY $w1
; SELECT-NEXT: [[DEF:%[0-9]+]]:fpr64 = IMPLICIT_DEF
; SELECT-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr64 = INSERT_SUBREG [[DEF]], %r, %subreg.ssub
; SELECT-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; SELECT-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[DEF]], %subreg.dsub
; SELECT-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 0, %r
; SELECT-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[INSERT_SUBREG]], %subreg.dsub
; SELECT-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, %q
; SELECT-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
; SELECT-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; SELECT-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub
; SELECT-NEXT: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, %q
; SELECT-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr1]].dsub
; SELECT-NEXT: $d0 = COPY [[COPY1]]
; SELECT-NEXT: $d0 = COPY [[COPY]]
; SELECT-NEXT: RET_ReallyLR implicit $d0
%r:_(s32) = COPY $w0
%q:_(s32) = COPY $w1
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/aarch64-bif-gen.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -76,8 +76,7 @@ define <1 x i32> @test_bitf_v1i32(<1 x i32> %A, <1 x i32> %B, <1 x i32> %C) {
; CHECK-GI-NEXT: bic w9, w9, w8
; CHECK-GI-NEXT: and w8, w8, w10
; CHECK-GI-NEXT: orr w8, w9, w8
; CHECK-GI-NEXT: mov v0.s[0], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: fmov s0, w8
; CHECK-GI-NEXT: ret
%neg = xor <1 x i32> %C, <i32 -1>
%and = and <1 x i32> %neg, %B
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -76,8 +76,7 @@ define <1 x i32> @test_bit_v1i32(<1 x i32> %A, <1 x i32> %B, <1 x i32> %C) {
; CHECK-GI-NEXT: and w9, w8, w9
; CHECK-GI-NEXT: bic w8, w10, w8
; CHECK-GI-NEXT: orr w8, w9, w8
; CHECK-GI-NEXT: mov v0.s[0], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: fmov s0, w8
; CHECK-GI-NEXT: ret
%and = and <1 x i32> %C, %B
%neg = xor <1 x i32> %C, <i32 -1>
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -204,7 +204,7 @@ define void @matrix_mul_double_shuffle(i32 %N, ptr nocapture %C, ptr nocapture r
; CHECK-GI-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-GI-NEXT: ldrh w9, [x2], #16
; CHECK-GI-NEXT: subs x8, x8, #8
; CHECK-GI-NEXT: mov v2.s[0], w9
; CHECK-GI-NEXT: fmov s2, w9
; CHECK-GI-NEXT: mov w9, w0
; CHECK-GI-NEXT: add w0, w0, #8
; CHECK-GI-NEXT: lsl x9, x9, #2
Expand Down
112 changes: 56 additions & 56 deletions llvm/test/CodeGen/AArch64/aarch64-smull.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2282,14 +2282,14 @@ define <2 x i64> @asr(<2 x i64> %a, <2 x i64> %b) {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #32
; CHECK-GI-NEXT: sshr v1.2d, v1.2d, #32
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: fmov x9, d1
; CHECK-GI-NEXT: mov x10, v0.d[1]
; CHECK-GI-NEXT: mov x11, v1.d[1]
; CHECK-GI-NEXT: fmov x10, d0
; CHECK-GI-NEXT: fmov x11, d1
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov x9, v1.d[1]
; CHECK-GI-NEXT: mul x10, x10, x11
; CHECK-GI-NEXT: mul x8, x8, x9
; CHECK-GI-NEXT: mul x9, x10, x11
; CHECK-GI-NEXT: mov v0.d[0], x8
; CHECK-GI-NEXT: mov v0.d[1], x9
; CHECK-GI-NEXT: fmov d0, x10
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: ret
%x = ashr <2 x i64> %a, <i64 32, i64 32>
%y = ashr <2 x i64> %b, <i64 32, i64 32>
Expand Down Expand Up @@ -2317,14 +2317,14 @@ define <2 x i64> @asr_const(<2 x i64> %a, <2 x i64> %b) {
; CHECK-GI-NEXT: adrp x8, .LCPI81_0
; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #32
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI81_0]
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: fmov x9, d1
; CHECK-GI-NEXT: mov x10, v0.d[1]
; CHECK-GI-NEXT: mov x11, v1.d[1]
; CHECK-GI-NEXT: fmov x10, d0
; CHECK-GI-NEXT: fmov x11, d1
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov x9, v1.d[1]
; CHECK-GI-NEXT: mul x10, x10, x11
; CHECK-GI-NEXT: mul x8, x8, x9
; CHECK-GI-NEXT: mul x9, x10, x11
; CHECK-GI-NEXT: mov v0.d[0], x8
; CHECK-GI-NEXT: mov v0.d[1], x9
; CHECK-GI-NEXT: fmov d0, x10
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: ret
%x = ashr <2 x i64> %a, <i64 32, i64 32>
%z = mul nsw <2 x i64> %x, <i64 31, i64 31>
Expand Down Expand Up @@ -2799,14 +2799,14 @@ define <2 x i64> @sdistribute_v2i32(<2 x i32> %src1, <2 x i32> %src2, <2 x i32>
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: sshll v2.2d, v2.2s, #0
; CHECK-GI-NEXT: saddl v0.2d, v0.2s, v1.2s
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: fmov x9, d2
; CHECK-GI-NEXT: mov x10, v0.d[1]
; CHECK-GI-NEXT: mov x11, v2.d[1]
; CHECK-GI-NEXT: fmov x10, d0
; CHECK-GI-NEXT: fmov x11, d2
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov x9, v2.d[1]
; CHECK-GI-NEXT: mul x10, x10, x11
; CHECK-GI-NEXT: mul x8, x8, x9
; CHECK-GI-NEXT: mul x9, x10, x11
; CHECK-GI-NEXT: mov v0.d[0], x8
; CHECK-GI-NEXT: mov v0.d[1], x9
; CHECK-GI-NEXT: fmov d0, x10
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: ret
entry:
%4 = sext <2 x i32> %src1 to <2 x i64>
Expand Down Expand Up @@ -2838,14 +2838,14 @@ define <2 x i64> @sdistribute_const1_v2i32(<2 x i32> %src1, <2 x i32> %mul) {
; CHECK-GI-NEXT: sshll v1.2d, v1.2s, #0
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI101_0]
; CHECK-GI-NEXT: saddw v0.2d, v2.2d, v0.2s
; CHECK-GI-NEXT: fmov x9, d1
; CHECK-GI-NEXT: mov x11, v1.d[1]
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov x10, v0.d[1]
; CHECK-GI-NEXT: fmov x11, d1
; CHECK-GI-NEXT: mov x9, v1.d[1]
; CHECK-GI-NEXT: fmov x10, d0
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mul x10, x10, x11
; CHECK-GI-NEXT: mul x8, x8, x9
; CHECK-GI-NEXT: mul x9, x10, x11
; CHECK-GI-NEXT: mov v0.d[0], x8
; CHECK-GI-NEXT: mov v0.d[1], x9
; CHECK-GI-NEXT: fmov d0, x10
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: ret
entry:
%4 = sext <2 x i32> %src1 to <2 x i64>
Expand Down Expand Up @@ -2875,14 +2875,14 @@ define <2 x i64> @sdistribute_const2_v2i32(<2 x i32> %src1, <2 x i32> %src2) {
; CHECK-GI-NEXT: adrp x8, .LCPI102_0
; CHECK-GI-NEXT: saddl v0.2d, v0.2s, v1.2s
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI102_0]
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: fmov x9, d1
; CHECK-GI-NEXT: mov x10, v0.d[1]
; CHECK-GI-NEXT: mov x11, v1.d[1]
; CHECK-GI-NEXT: fmov x10, d0
; CHECK-GI-NEXT: fmov x11, d1
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov x9, v1.d[1]
; CHECK-GI-NEXT: mul x10, x10, x11
; CHECK-GI-NEXT: mul x8, x8, x9
; CHECK-GI-NEXT: mul x9, x10, x11
; CHECK-GI-NEXT: mov v0.d[0], x8
; CHECK-GI-NEXT: mov v0.d[1], x9
; CHECK-GI-NEXT: fmov d0, x10
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: ret
entry:
%4 = sext <2 x i32> %src1 to <2 x i64>
Expand All @@ -2909,14 +2909,14 @@ define <2 x i64> @udistribute_v2i32(<2 x i32> %src1, <2 x i32> %src2, <2 x i32>
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ushll v2.2d, v2.2s, #0
; CHECK-GI-NEXT: uaddl v0.2d, v0.2s, v1.2s
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: fmov x9, d2
; CHECK-GI-NEXT: mov x10, v0.d[1]
; CHECK-GI-NEXT: mov x11, v2.d[1]
; CHECK-GI-NEXT: fmov x10, d0
; CHECK-GI-NEXT: fmov x11, d2
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov x9, v2.d[1]
; CHECK-GI-NEXT: mul x10, x10, x11
; CHECK-GI-NEXT: mul x8, x8, x9
; CHECK-GI-NEXT: mul x9, x10, x11
; CHECK-GI-NEXT: mov v0.d[0], x8
; CHECK-GI-NEXT: mov v0.d[1], x9
; CHECK-GI-NEXT: fmov d0, x10
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: ret
entry:
%4 = zext <2 x i32> %src1 to <2 x i64>
Expand Down Expand Up @@ -2948,14 +2948,14 @@ define <2 x i64> @udistribute_const1_v2i32(<2 x i32> %src1, <2 x i32> %mul) {
; CHECK-GI-NEXT: ushll v1.2d, v1.2s, #0
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI104_0]
; CHECK-GI-NEXT: uaddw v0.2d, v2.2d, v0.2s
; CHECK-GI-NEXT: fmov x9, d1
; CHECK-GI-NEXT: mov x11, v1.d[1]
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov x10, v0.d[1]
; CHECK-GI-NEXT: fmov x11, d1
; CHECK-GI-NEXT: mov x9, v1.d[1]
; CHECK-GI-NEXT: fmov x10, d0
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mul x10, x10, x11
; CHECK-GI-NEXT: mul x8, x8, x9
; CHECK-GI-NEXT: mul x9, x10, x11
; CHECK-GI-NEXT: mov v0.d[0], x8
; CHECK-GI-NEXT: mov v0.d[1], x9
; CHECK-GI-NEXT: fmov d0, x10
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: ret
entry:
%4 = zext <2 x i32> %src1 to <2 x i64>
Expand Down Expand Up @@ -2985,14 +2985,14 @@ define <2 x i64> @udistribute_const2_v2i32(<2 x i32> %src1, <2 x i32> %src2) {
; CHECK-GI-NEXT: adrp x8, .LCPI105_0
; CHECK-GI-NEXT: uaddl v0.2d, v0.2s, v1.2s
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI105_0]
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: fmov x9, d1
; CHECK-GI-NEXT: mov x10, v0.d[1]
; CHECK-GI-NEXT: mov x11, v1.d[1]
; CHECK-GI-NEXT: fmov x10, d0
; CHECK-GI-NEXT: fmov x11, d1
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov x9, v1.d[1]
; CHECK-GI-NEXT: mul x10, x10, x11
; CHECK-GI-NEXT: mul x8, x8, x9
; CHECK-GI-NEXT: mul x9, x10, x11
; CHECK-GI-NEXT: mov v0.d[0], x8
; CHECK-GI-NEXT: mov v0.d[1], x9
; CHECK-GI-NEXT: fmov d0, x10
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: ret
entry:
%4 = zext <2 x i32> %src1 to <2 x i64>
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/abs.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -247,8 +247,7 @@ define <1 x i32> @abs_v1i32(<1 x i32> %a){
; CHECK-GI-NEXT: fmov w9, s0
; CHECK-GI-NEXT: cmp w8, #0
; CHECK-GI-NEXT: cneg w8, w9, le
; CHECK-GI-NEXT: mov v0.s[0], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: fmov s0, w8
; CHECK-GI-NEXT: ret
entry:
%res = call <1 x i32> @llvm.abs.v1i32(<1 x i32> %a, i1 0)
Expand Down
57 changes: 18 additions & 39 deletions llvm/test/CodeGen/AArch64/arm64-dup.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -334,40 +334,25 @@ entry:
}

define <2 x i32> @f(i32 %a, i32 %b) nounwind readnone {
; CHECK-SD-LABEL: f:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fmov s0, w0
; CHECK-SD-NEXT: mov.s v0[1], w1
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: f:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov.s v0[0], w0
; CHECK-GI-NEXT: mov.s v0[1], w1
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
; CHECK-LABEL: f:
; CHECK: // %bb.0:
; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: mov.s v0[1], w1
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%vecinit = insertelement <2 x i32> undef, i32 %a, i32 0
%vecinit1 = insertelement <2 x i32> %vecinit, i32 %b, i32 1
ret <2 x i32> %vecinit1
}

define <4 x i32> @g(i32 %a, i32 %b) nounwind readnone {
; CHECK-SD-LABEL: g:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fmov s0, w0
; CHECK-SD-NEXT: mov.s v0[1], w1
; CHECK-SD-NEXT: mov.s v0[2], w1
; CHECK-SD-NEXT: mov.s v0[3], w0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: g:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov.s v0[0], w0
; CHECK-GI-NEXT: mov.s v0[1], w1
; CHECK-GI-NEXT: mov.s v0[2], w1
; CHECK-GI-NEXT: mov.s v0[3], w0
; CHECK-GI-NEXT: ret
; CHECK-LABEL: g:
; CHECK: // %bb.0:
; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: mov.s v0[1], w1
; CHECK-NEXT: mov.s v0[2], w1
; CHECK-NEXT: mov.s v0[3], w0
; CHECK-NEXT: ret
%vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
%vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
%vecinit2 = insertelement <4 x i32> %vecinit1, i32 %b, i32 2
Expand All @@ -376,17 +361,11 @@ define <4 x i32> @g(i32 %a, i32 %b) nounwind readnone {
}

define <2 x i64> @h(i64 %a, i64 %b) nounwind readnone {
; CHECK-SD-LABEL: h:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fmov d0, x0
; CHECK-SD-NEXT: mov.d v0[1], x1
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: h:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov.d v0[0], x0
; CHECK-GI-NEXT: mov.d v0[1], x1
; CHECK-GI-NEXT: ret
; CHECK-LABEL: h:
; CHECK: // %bb.0:
; CHECK-NEXT: fmov d0, x0
; CHECK-NEXT: mov.d v0[1], x1
; CHECK-NEXT: ret
%vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
%vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
ret <2 x i64> %vecinit1
Expand Down
Loading