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[ARM] Add neon vector support for floor #142559

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[ARM] Add neon vector support for floor #142559

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4 changes: 2 additions & 2 deletions clang/lib/CodeGen/TargetBuiltins/ARM.cpp
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Expand Up @@ -843,8 +843,8 @@ static const ARMVectorIntrinsicInfo ARMSIMDIntrinsicMap [] = {
NEONMAP1(vrndaq_v, arm_neon_vrinta, Add1ArgType),
NEONMAP0(vrndi_v),
NEONMAP0(vrndiq_v),
NEONMAP1(vrndm_v, arm_neon_vrintm, Add1ArgType),
NEONMAP1(vrndmq_v, arm_neon_vrintm, Add1ArgType),
NEONMAP1(vrndm_v, floor, Add1ArgType),
NEONMAP1(vrndmq_v, floor, Add1ArgType),
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For AArch64, we have C++ code that chooses between llvm.floor and llvm.experimental.constrained.floor. Do we want the same for 32-bit?

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I don't believe anyone has made constrained intrinsics work for AArch32.

NEONMAP1(vrndn_v, arm_neon_vrintn, Add1ArgType),
NEONMAP1(vrndnq_v, arm_neon_vrintn, Add1ArgType),
NEONMAP1(vrndp_v, arm_neon_vrintp, Add1ArgType),
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4 changes: 2 additions & 2 deletions clang/test/CodeGen/arm-neon-directed-rounding.c
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Expand Up @@ -66,7 +66,7 @@ float32x4_t test_vrndaq_f32(float32x4_t a) {
// CHECK-A32-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
// CHECK-A32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
// CHECK-A32-NEXT: [[VRNDM_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
// CHECK-A32-NEXT: [[VRNDM_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintm.v2f32(<2 x float> [[VRNDM_V_I]])
// CHECK-A32-NEXT: [[VRNDM_V1_I:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[VRNDM_V_I]])
// CHECK-A32-NEXT: [[VRNDM_V2_I:%.*]] = bitcast <2 x float> [[VRNDM_V1_I]] to <8 x i8>
// CHECK-A32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRNDM_V2_I]] to <2 x i32>
// CHECK-A32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <2 x float>
Expand All @@ -91,7 +91,7 @@ float32x2_t test_vrndm_f32(float32x2_t a) {
// CHECK-A32-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
// CHECK-A32-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
// CHECK-A32-NEXT: [[VRNDMQ_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
// CHECK-A32-NEXT: [[VRNDMQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintm.v4f32(<4 x float> [[VRNDMQ_V_I]])
// CHECK-A32-NEXT: [[VRNDMQ_V1_I:%.*]] = call <4 x float> @llvm.floor.v4f32(<4 x float> [[VRNDMQ_V_I]])
// CHECK-A32-NEXT: [[VRNDMQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDMQ_V1_I]] to <16 x i8>
// CHECK-A32-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRNDMQ_V2_I]] to <4 x i32>
// CHECK-A32-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to <4 x float>
Expand Down
4 changes: 2 additions & 2 deletions clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
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Expand Up @@ -586,7 +586,7 @@ float16x8_t test_vrndaq_f16(float16x8_t a) {
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
// CHECK-NEXT: [[VRNDM_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
// CHECK-NEXT: [[VRNDM_V1_I:%.*]] = call <4 x half> @llvm.arm.neon.vrintm.v4f16(<4 x half> [[VRNDM_V_I]])
// CHECK-NEXT: [[VRNDM_V1_I:%.*]] = call <4 x half> @llvm.floor.v4f16(<4 x half> [[VRNDM_V_I]])
// CHECK-NEXT: [[VRNDM_V2_I:%.*]] = bitcast <4 x half> [[VRNDM_V1_I]] to <8 x i8>
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRNDM_V2_I]] to <4 x i16>
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to <4 x half>
Expand All @@ -602,7 +602,7 @@ float16x4_t test_vrndm_f16(float16x4_t a) {
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>
// CHECK-NEXT: [[VRNDMQ_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
// CHECK-NEXT: [[VRNDMQ_V1_I:%.*]] = call <8 x half> @llvm.arm.neon.vrintm.v8f16(<8 x half> [[VRNDMQ_V_I]])
// CHECK-NEXT: [[VRNDMQ_V1_I:%.*]] = call <8 x half> @llvm.floor.v8f16(<8 x half> [[VRNDMQ_V_I]])
// CHECK-NEXT: [[VRNDMQ_V2_I:%.*]] = bitcast <8 x half> [[VRNDMQ_V1_I]] to <16 x i8>
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRNDMQ_V2_I]] to <8 x i16>
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to <8 x half>
Expand Down
1 change: 0 additions & 1 deletion llvm/include/llvm/IR/IntrinsicsARM.td
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Expand Up @@ -682,7 +682,6 @@ def int_arm_neon_vrintn : Neon_1FloatArg_Intrinsic;
def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;

// De-interleaving vector loads from N-element structures.
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1 change: 1 addition & 0 deletions llvm/lib/IR/AutoUpgrade.cpp
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Expand Up @@ -719,6 +719,7 @@ static bool upgradeArmOrAarch64IntrinsicFunction(bool IsArm, Function *F,
.StartsWith("vqaddu.", Intrinsic::uadd_sat)
.StartsWith("vqsubs.", Intrinsic::ssub_sat)
.StartsWith("vqsubu.", Intrinsic::usub_sat)
.StartsWith("vrintm.", Intrinsic::floor)
.Default(Intrinsic::not_intrinsic);
if (ID != Intrinsic::not_intrinsic) {
NewFn = Intrinsic::getOrInsertDeclaration(F->getParent(), ID,
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8 changes: 8 additions & 0 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
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Expand Up @@ -1598,6 +1598,11 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);

if (Subtarget->hasV8Ops()) {
setOperationAction(ISD::FFLOOR, MVT::v2f32, Legal);
setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
}

if (Subtarget->hasFullFP16()) {
setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
Expand All @@ -1608,6 +1613,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);

setOperationAction(ISD::FFLOOR, MVT::v4f16, Legal);
setOperationAction(ISD::FFLOOR, MVT::v8f16, Legal);
}
}

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2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMInstrNEON.td
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Expand Up @@ -7316,7 +7316,7 @@ defm VRINTNN : VRINT_FPI<"n", 0b000, int_arm_neon_vrintn>;
defm VRINTXN : VRINT_FPI<"x", 0b001, int_arm_neon_vrintx>;
defm VRINTAN : VRINT_FPI<"a", 0b010, int_arm_neon_vrinta>;
defm VRINTZN : VRINT_FPI<"z", 0b011, int_arm_neon_vrintz>;
defm VRINTMN : VRINT_FPI<"m", 0b101, int_arm_neon_vrintm>;
defm VRINTMN : VRINT_FPI<"m", 0b101, ffloor>;
defm VRINTPN : VRINT_FPI<"p", 0b111, int_arm_neon_vrintp>;

// Cryptography instructions
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56 changes: 4 additions & 52 deletions llvm/test/CodeGen/ARM/vrint.ll
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Expand Up @@ -813,21 +813,7 @@ define <4 x half> @frintm_4h(<4 x half> %A) nounwind {
;
; CHECK-FP16-LABEL: frintm_4h:
; CHECK-FP16: @ %bb.0:
; CHECK-FP16-NEXT: vmovx.f16 s2, s0
; CHECK-FP16-NEXT: vrintm.f16 s2, s2
; CHECK-FP16-NEXT: vmov r0, s2
; CHECK-FP16-NEXT: vrintm.f16 s2, s0
; CHECK-FP16-NEXT: vmov r1, s2
; CHECK-FP16-NEXT: vrintm.f16 s2, s1
; CHECK-FP16-NEXT: vmovx.f16 s0, s1
; CHECK-FP16-NEXT: vrintm.f16 s0, s0
; CHECK-FP16-NEXT: vmov.16 d16[0], r1
; CHECK-FP16-NEXT: vmov.16 d16[1], r0
; CHECK-FP16-NEXT: vmov r0, s2
; CHECK-FP16-NEXT: vmov.16 d16[2], r0
; CHECK-FP16-NEXT: vmov r0, s0
; CHECK-FP16-NEXT: vmov.16 d16[3], r0
; CHECK-FP16-NEXT: vorr d0, d16, d16
; CHECK-FP16-NEXT: vrintm.f16 d0, d0
; CHECK-FP16-NEXT: bx lr
%tmp3 = call <4 x half> @llvm.floor.v4f16(<4 x half> %A)
ret <4 x half> %tmp3
Expand Down Expand Up @@ -977,35 +963,7 @@ define <8 x half> @frintm_8h(<8 x half> %A) nounwind {
;
; CHECK-FP16-LABEL: frintm_8h:
; CHECK-FP16: @ %bb.0:
; CHECK-FP16-NEXT: vmovx.f16 s4, s2
; CHECK-FP16-NEXT: vrintm.f16 s4, s4
; CHECK-FP16-NEXT: vmov r0, s4
; CHECK-FP16-NEXT: vrintm.f16 s4, s2
; CHECK-FP16-NEXT: vmov r1, s4
; CHECK-FP16-NEXT: vrintm.f16 s4, s3
; CHECK-FP16-NEXT: vmov.16 d17[0], r1
; CHECK-FP16-NEXT: vmov.16 d17[1], r0
; CHECK-FP16-NEXT: vmov r0, s4
; CHECK-FP16-NEXT: vmovx.f16 s4, s3
; CHECK-FP16-NEXT: vrintm.f16 s4, s4
; CHECK-FP16-NEXT: vmov.16 d17[2], r0
; CHECK-FP16-NEXT: vmov r0, s4
; CHECK-FP16-NEXT: vmovx.f16 s4, s0
; CHECK-FP16-NEXT: vrintm.f16 s4, s4
; CHECK-FP16-NEXT: vmov.16 d17[3], r0
; CHECK-FP16-NEXT: vmov r0, s4
; CHECK-FP16-NEXT: vrintm.f16 s4, s0
; CHECK-FP16-NEXT: vmovx.f16 s0, s1
; CHECK-FP16-NEXT: vmov r1, s4
; CHECK-FP16-NEXT: vrintm.f16 s4, s1
; CHECK-FP16-NEXT: vrintm.f16 s0, s0
; CHECK-FP16-NEXT: vmov.16 d16[0], r1
; CHECK-FP16-NEXT: vmov.16 d16[1], r0
; CHECK-FP16-NEXT: vmov r0, s4
; CHECK-FP16-NEXT: vmov.16 d16[2], r0
; CHECK-FP16-NEXT: vmov r0, s0
; CHECK-FP16-NEXT: vmov.16 d16[3], r0
; CHECK-FP16-NEXT: vorr q0, q8, q8
; CHECK-FP16-NEXT: vrintm.f16 q0, q0
; CHECK-FP16-NEXT: bx lr
%tmp3 = call <8 x half> @llvm.floor.v8f16(<8 x half> %A)
ret <8 x half> %tmp3
Expand All @@ -1031,9 +989,7 @@ define <2 x float> @frintm_2s(<2 x float> %A) nounwind {
;
; CHECK-LABEL: frintm_2s:
; CHECK: @ %bb.0:
; CHECK-NEXT: vrintm.f32 s3, s1
; CHECK-NEXT: vrintm.f32 s2, s0
; CHECK-NEXT: vmov.f64 d0, d1
; CHECK-NEXT: vrintm.f32 d0, d0
; CHECK-NEXT: bx lr
%tmp3 = call <2 x float> @llvm.floor.v2f32(<2 x float> %A)
ret <2 x float> %tmp3
Expand Down Expand Up @@ -1065,11 +1021,7 @@ define <4 x float> @frintm_4s(<4 x float> %A) nounwind {
;
; CHECK-LABEL: frintm_4s:
; CHECK: @ %bb.0:
; CHECK-NEXT: vrintm.f32 s7, s3
; CHECK-NEXT: vrintm.f32 s6, s2
; CHECK-NEXT: vrintm.f32 s5, s1
; CHECK-NEXT: vrintm.f32 s4, s0
; CHECK-NEXT: vorr q0, q1, q1
; CHECK-NEXT: vrintm.f32 q0, q0
; CHECK-NEXT: bx lr
%tmp3 = call <4 x float> @llvm.floor.v4f32(<4 x float> %A)
ret <4 x float> %tmp3
Expand Down
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