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[Clang][PowerPC] Add __dmr type and DMF integer calculation builtins #142480

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[Clang][PowerPC] Add __dmr type and DMF integer calculation builtins #142480

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12 changes: 12 additions & 0 deletions clang/include/clang/Basic/BuiltinsPPC.def
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Expand Up @@ -1134,6 +1134,18 @@ UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2np, "vW512*VVi15i15i3", true,
"mma,paired-vector-memops")
UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2nn, "vW512*VVi15i15i3", true,
"mma,paired-vector-memops")
UNALIASED_CUSTOM_BUILTIN(mma_dmxvi8gerx4, "vW1024*W256V", false,
"mma,paired-vector-memops")
UNALIASED_CUSTOM_BUILTIN(mma_pmdmxvi8gerx4, "vW1024*W256Vi255i15i15", false,
"mma,paired-vector-memops")
UNALIASED_CUSTOM_BUILTIN(mma_dmxvi8gerx4pp, "vW1024*W256V", true,
"mma,paired-vector-memops")
UNALIASED_CUSTOM_BUILTIN(mma_pmdmxvi8gerx4pp, "vW1024*W256Vi255i15i15", true,
"mma,paired-vector-memops")
UNALIASED_CUSTOM_BUILTIN(mma_dmxvi8gerx4spp, "vW1024*W256V", true,
"mma,paired-vector-memops")
UNALIASED_CUSTOM_BUILTIN(mma_pmdmxvi8gerx4spp, "vW1024*W256Vi255i15i15", true,
"mma,paired-vector-memops")

// FIXME: Obviously incomplete.

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1 change: 1 addition & 0 deletions clang/include/clang/Basic/PPCTypes.def
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Expand Up @@ -30,6 +30,7 @@
#endif


PPC_VECTOR_MMA_TYPE(__dmr, VectorDmr, 1024)
PPC_VECTOR_MMA_TYPE(__vector_quad, VectorQuad, 512)
PPC_VECTOR_VSX_TYPE(__vector_pair, VectorPair, 256)

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1 change: 1 addition & 0 deletions clang/lib/AST/ASTContext.cpp
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Expand Up @@ -3455,6 +3455,7 @@ static void encodeTypeForFunctionPointerAuth(const ASTContext &Ctx,
case BuiltinType::BFloat16:
case BuiltinType::VectorQuad:
case BuiltinType::VectorPair:
case BuiltinType::VectorDmr:
OS << "?";
return;

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13 changes: 10 additions & 3 deletions clang/test/AST/ast-dump-ppc-types.c
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@@ -1,9 +1,11 @@
// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu future \
// RUN: -ast-dump %s | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
// RUN: -ast-dump -ast-dump-filter __vector %s | FileCheck %s
// RUN: -ast-dump %s | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr9 \
// RUN: -ast-dump -ast-dump-filter __vector %s | FileCheck %s
// RUN: -ast-dump %s | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr8 \
// RUN: -ast-dump -ast-dump-filter __vector %s | FileCheck %s
// RUN: -ast-dump %s | FileCheck %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -ast-dump %s | FileCheck %s \
// RUN: --check-prefix=CHECK-X86_64
// RUN: %clang_cc1 -triple arm-unknown-unknown -ast-dump %s | FileCheck %s \
Expand All @@ -15,16 +17,21 @@
// are correctly defined. We also added checks on a couple of other targets to
// ensure the types are target-dependent.

// CHECK: TypedefDecl {{.*}} implicit __dmr '__dmr'
// CHECK: `-BuiltinType {{.*}} '__dmr'
// CHECK: TypedefDecl {{.*}} implicit __vector_quad '__vector_quad'
// CHECK-NEXT: -BuiltinType {{.*}} '__vector_quad'
// CHECK: TypedefDecl {{.*}} implicit __vector_pair '__vector_pair'
// CHECK-NEXT: -BuiltinType {{.*}} '__vector_pair'

// CHECK-X86_64-NOT: __dmr
// CHECK-X86_64-NOT: __vector_quad
// CHECK-X86_64-NOT: __vector_pair

// CHECK-ARM-NOT: __dmr
// CHECK-ARM-NOT: __vector_quad
// CHECK-ARM-NOT: __vector_pair

// CHECK-RISCV64-NOT: __dmr
// CHECK-RISCV64-NOT: __vector_quad
// CHECK-RISCV64-NOT: __vector_pair
94 changes: 94 additions & 0 deletions clang/test/CodeGen/PowerPC/builtins-ppc-mmaplus.c
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@@ -0,0 +1,94 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future \
// RUN: -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -O3 -triple powerpc64-ibm-aix -target-cpu future \
// RUN: -emit-llvm %s -o - | FileCheck %s


// CHECK-LABEL: @test_dmxvi8gerx4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2:![0-9]+]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4(<256 x i1> [[TMP0]], <16 x i8> [[VC:%.*]])
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6:![0-9]+]]
// CHECK-NEXT: ret void
//
void test_dmxvi8gerx4(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
__dmr vdmr = *((__dmr *)vdmrp);
__vector_pair vp = *((__vector_pair *)vpp);
__builtin_mma_dmxvi8gerx4(&vdmr, vp, vc);
*((__dmr *)resp) = vdmr;
}

// CHECK-LABEL: @test_pmdmxvi8gerx4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4(<256 x i1> [[TMP0]], <16 x i8> [[VC:%.*]], i32 0, i32 0, i32 0)
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
// CHECK-NEXT: ret void
//
void test_pmdmxvi8gerx4(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
__dmr vdmr = *((__dmr *)vdmrp);
__vector_pair vp = *((__vector_pair *)vpp);
__builtin_mma_pmdmxvi8gerx4(&vdmr, vp, vc, 0, 0, 0);
*((__dmr *)resp) = vdmr;
}

// CHECK-LABEL: @test_dmxvi8gerx4pp(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4pp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]])
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
// CHECK-NEXT: ret void
//
void test_dmxvi8gerx4pp(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
__dmr vdmr = *((__dmr *)vdmrp);
__vector_pair vp = *((__vector_pair *)vpp);
__builtin_mma_dmxvi8gerx4pp(&vdmr, vp, vc);
*((__dmr *)resp) = vdmr;
}

// CHECK-LABEL: @test_pmdmxvi8gerx4pp(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4pp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], i32 0, i32 0, i32 0)
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
// CHECK-NEXT: ret void
//
void test_pmdmxvi8gerx4pp(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
__dmr vdmr = *((__dmr *)vdmrp);
__vector_pair vp = *((__vector_pair *)vpp);
__builtin_mma_pmdmxvi8gerx4pp(&vdmr, vp, vc, 0, 0, 0);
*((__dmr *)resp) = vdmr;
}

// CHECK-LABEL: @test_dmxvi8gerx4spp(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4spp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]])
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
// CHECK-NEXT: ret void
//
void test_dmxvi8gerx4spp(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
__dmr vdmr = *((__dmr *)vdmrp);
__vector_pair vp = *((__vector_pair *)vpp);
__builtin_mma_dmxvi8gerx4spp(&vdmr, vp, vc);
*((__dmr *)resp) = vdmr;
}

// CHECK-LABEL: @test_pmdmxvi8gerx4spp(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load <1024 x i1>, ptr [[VDMRP:%.*]], align 128, !tbaa [[TBAA6]]
// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, ptr [[VPP:%.*]], align 32, !tbaa [[TBAA2]]
// CHECK-NEXT: [[TMP2:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.pmdmxvi8gerx4spp(<1024 x i1> [[TMP0]], <256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], i32 0, i32 0, i32 0)
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[RESP:%.*]], align 128, !tbaa [[TBAA6]]
// CHECK-NEXT: ret void
//
void test_pmdmxvi8gerx4spp(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
__dmr vdmr = *((__dmr *)vdmrp);
__vector_pair vp = *((__vector_pair *)vpp);
__builtin_mma_pmdmxvi8gerx4spp(&vdmr, vp, vc, 0, 0, 0);
*((__dmr *)resp) = vdmr;
}
21 changes: 21 additions & 0 deletions clang/test/CodeGen/PowerPC/ppc-future-mma-builtin-err.c
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@@ -0,0 +1,21 @@
// RUN: not %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-cpu future \
// RUN: %s -emit-llvm-only 2>&1 | FileCheck %s

__attribute__((target("no-mma")))
void test_mma(unsigned char *vdmrp, unsigned char *vpp, vector unsigned char vc) {
__dmr vdmr = *((__dmr *)vdmrp);
__vector_pair vp = *((__vector_pair *)vpp);
__builtin_mma_dmxvi8gerx4(&vdmr, vp, vc);
__builtin_mma_pmdmxvi8gerx4(&vdmr, vp, vc, 0, 0, 0);
__builtin_mma_dmxvi8gerx4pp(&vdmr, vp, vc);
__builtin_mma_pmdmxvi8gerx4pp(&vdmr, vp, vc, 0, 0, 0);
__builtin_mma_dmxvi8gerx4spp(&vdmr, vp, vc);
__builtin_mma_pmdmxvi8gerx4spp(&vdmr, vp, vc, 0, 0, 0);

// CHECK: error: '__builtin_mma_dmxvi8gerx4' needs target feature mma,paired-vector-memops
// CHECK: error: '__builtin_mma_pmdmxvi8gerx4' needs target feature mma,paired-vector-memops
// CHECK: error: '__builtin_mma_dmxvi8gerx4pp' needs target feature mma,paired-vector-memops
// CHECK: error: '__builtin_mma_pmdmxvi8gerx4pp' needs target feature mma,paired-vector-memops
// CHECK: error: '__builtin_mma_dmxvi8gerx4spp' needs target feature mma,paired-vector-memops
// CHECK: error: '__builtin_mma_pmdmxvi8gerx4spp' needs target feature mma,paired-vector-memops
}
20 changes: 20 additions & 0 deletions clang/test/CodeGen/PowerPC/ppc-future-paired-vec-memops-builtin-err.c
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@@ -0,0 +1,20 @@
// RUN: not %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-cpu future \
// RUN: %s -emit-llvm-only 2>&1 | FileCheck %s

__attribute__((target("no-paired-vector-memops")))
void test_pair(unsigned char *vdmr, unsigned char *vpp, vector unsigned char vc) {
__vector_pair vp = *((__vector_pair *)vpp);
__builtin_mma_dmxvi8gerx4((__dmr *)vdmr, vp, vc);
__builtin_mma_pmdmxvi8gerx4((__dmr *)vdmr, vp, vc, 0, 0, 0);
__builtin_mma_dmxvi8gerx4pp((__dmr *)vdmr, vp, vc);
__builtin_mma_pmdmxvi8gerx4pp((__dmr *)vdmr, vp, vc, 0, 0, 0);
__builtin_mma_dmxvi8gerx4spp((__dmr *)vdmr, vp, vc);
__builtin_mma_pmdmxvi8gerx4spp((__dmr *)vdmr, vp, vc, 0, 0, 0);

// CHECK: error: '__builtin_mma_dmxvi8gerx4' needs target feature mma,paired-vector-memops
// CHECK: error: '__builtin_mma_pmdmxvi8gerx4' needs target feature mma,paired-vector-memops
// CHECK: error: '__builtin_mma_dmxvi8gerx4pp' needs target feature mma,paired-vector-memops
// CHECK: error: '__builtin_mma_pmdmxvi8gerx4pp' needs target feature mma,paired-vector-memops
// CHECK: error: '__builtin_mma_dmxvi8gerx4spp' needs target feature mma,paired-vector-memops
// CHECK: error: '__builtin_mma_pmdmxvi8gerx4spp' needs target feature mma,paired-vector-memops
}
184 changes: 184 additions & 0 deletions clang/test/CodeGen/PowerPC/ppc-mmaplus-types.c
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future \
// RUN: -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr10 \
// RUN: -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr9 \
// RUN: -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr8 \
// RUN: -emit-llvm -o - %s | FileCheck %s

typedef __vector_quad vq_t;

// CHECK-LABEL: @test_dmr_copy(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[PTR1_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[PTR2_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[PTR1:%.*]], ptr [[PTR1_ADDR]], align 8
// CHECK-NEXT: store ptr [[PTR2:%.*]], ptr [[PTR2_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR1_ADDR]], align 8
// CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds <1024 x i1>, ptr [[TMP0]], i64 2
// CHECK-NEXT: [[TMP1:%.*]] = load <1024 x i1>, ptr [[ADD_PTR]], align 128
// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[PTR2_ADDR]], align 8
// CHECK-NEXT: [[ADD_PTR1:%.*]] = getelementptr inbounds <1024 x i1>, ptr [[TMP2]], i64 1
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr [[ADD_PTR1]], align 128
// CHECK-NEXT: ret void
//
void test_dmr_copy(__dmr *ptr1, __dmr *ptr2) {
*(ptr2 + 1) = *(ptr1 + 2);
}

// CHECK-LABEL: @test_dmr_typedef(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[INP_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[OUTP_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[VDMRIN:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[VDMROUT:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[INP:%.*]], ptr [[INP_ADDR]], align 8
// CHECK-NEXT: store ptr [[OUTP:%.*]], ptr [[OUTP_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[INP_ADDR]], align 8
// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRIN]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OUTP_ADDR]], align 8
// CHECK-NEXT: store ptr [[TMP1]], ptr [[VDMROUT]], align 8
// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VDMRIN]], align 8
// CHECK-NEXT: [[TMP3:%.*]] = load <1024 x i1>, ptr [[TMP2]], align 128
// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VDMROUT]], align 8
// CHECK-NEXT: store <1024 x i1> [[TMP3]], ptr [[TMP4]], align 128
// CHECK-NEXT: ret void
//
void test_dmr_typedef(int *inp, int *outp) {
__dmr *vdmrin = (__dmr *)inp;
__dmr *vdmrout = (__dmr *)outp;
*vdmrout = *vdmrin;
}

// CHECK-LABEL: @test_dmr_arg(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[VDMR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[VDMRP:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[VDMR:%.*]], ptr [[VDMR_ADDR]], align 8
// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRP]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMR_ADDR]], align 8
// CHECK-NEXT: [[TMP2:%.*]] = load <1024 x i1>, ptr [[TMP1]], align 128
// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VDMRP]], align 8
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[TMP3]], align 128
// CHECK-NEXT: ret void
//
void test_dmr_arg(__dmr *vdmr, int *ptr) {
__dmr *vdmrp = (__dmr *)ptr;
*vdmrp = *vdmr;
}

// CHECK-LABEL: @test_dmr_const_arg(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[VDMR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[VDMRP:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[VDMR:%.*]], ptr [[VDMR_ADDR]], align 8
// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRP]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMR_ADDR]], align 8
// CHECK-NEXT: [[TMP2:%.*]] = load <1024 x i1>, ptr [[TMP1]], align 128
// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VDMRP]], align 8
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[TMP3]], align 128
// CHECK-NEXT: ret void
//
void test_dmr_const_arg(const __dmr *const vdmr, int *ptr) {
__dmr *vdmrp = (__dmr *)ptr;
*vdmrp = *vdmr;
}

// CHECK-LABEL: @test_dmr_array_arg(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[VDMRA_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[VDMRP:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[VDMRA:%.*]], ptr [[VDMRA_ADDR]], align 8
// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRP]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMRA_ADDR]], align 8
// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds <1024 x i1>, ptr [[TMP1]], i64 0
// CHECK-NEXT: [[TMP2:%.*]] = load <1024 x i1>, ptr [[ARRAYIDX]], align 128
// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VDMRP]], align 8
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[TMP3]], align 128
// CHECK-NEXT: ret void
//
void test_dmr_array_arg(__dmr vdmra[], int *ptr) {
__dmr *vdmrp = (__dmr *)ptr;
*vdmrp = vdmra[0];
}

// CHECK-LABEL: @test_dmr_ret(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[VDMRP:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRP]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMRP]], align 8
// CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds <1024 x i1>, ptr [[TMP1]], i64 2
// CHECK-NEXT: ret ptr [[ADD_PTR]]
//
__dmr *test_dmr_ret(int *ptr) {
__dmr *vdmrp = (__dmr *)ptr;
return vdmrp + 2;
}

// CHECK-LABEL: @test_dmr_ret_const(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[VDMRP:%.*]] = alloca ptr, align 8
// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRP]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMRP]], align 8
// CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds <1024 x i1>, ptr [[TMP1]], i64 2
// CHECK-NEXT: ret ptr [[ADD_PTR]]
//
const __dmr *test_dmr_ret_const(int *ptr) {
__dmr *vdmrp = (__dmr *)ptr;
return vdmrp + 2;
}

// CHECK-LABEL: @test_dmr_sizeof_alignof(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[VDMRP:%.*]] = alloca ptr, align 8
// CHECK-NEXT: [[VDMR:%.*]] = alloca <1024 x i1>, align 128
// CHECK-NEXT: [[SIZET:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[ALIGNT:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[SIZEV:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[ALIGNV:%.*]] = alloca i32, align 4
// CHECK-NEXT: store ptr [[PTR:%.*]], ptr [[PTR_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
// CHECK-NEXT: store ptr [[TMP0]], ptr [[VDMRP]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VDMRP]], align 8
// CHECK-NEXT: [[TMP2:%.*]] = load <1024 x i1>, ptr [[TMP1]], align 128
// CHECK-NEXT: store <1024 x i1> [[TMP2]], ptr [[VDMR]], align 128
// CHECK-NEXT: store i32 128, ptr [[SIZET]], align 4
// CHECK-NEXT: store i32 128, ptr [[ALIGNT]], align 4
// CHECK-NEXT: store i32 128, ptr [[SIZEV]], align 4
// CHECK-NEXT: store i32 128, ptr [[ALIGNV]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIZET]], align 4
// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ALIGNT]], align 4
// CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP3]], [[TMP4]]
// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIZEV]], align 4
// CHECK-NEXT: [[ADD1:%.*]] = add i32 [[ADD]], [[TMP5]]
// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ALIGNV]], align 4
// CHECK-NEXT: [[ADD2:%.*]] = add i32 [[ADD1]], [[TMP6]]
// CHECK-NEXT: ret i32 [[ADD2]]
//
int test_dmr_sizeof_alignof(int *ptr) {
__dmr *vdmrp = (__dmr *)ptr;
__dmr vdmr = *vdmrp;
unsigned sizet = sizeof(__dmr);
unsigned alignt = __alignof__(__dmr);
unsigned sizev = sizeof(vdmr);
unsigned alignv = __alignof__(vdmr);
return sizet + alignt + sizev + alignv;
}
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