Skip to content

[RISCV] Select signed bitfield extracts for XAndesPerf #142303

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Jun 3, 2025
Merged

[RISCV] Select signed bitfield extracts for XAndesPerf #142303

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
deb0edc
[RISCV] Pre-commit
tclin914 Jun 1, 2025
36a3d51
[RISCV] Select signed bitfield extracts for XAndesPerf
tclin914 Jun 1, 2025
f31f0ff
Remove i64 type testcase from rv32xandesperf.ll
tclin914 Jun 3, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 5 additions & 3 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -601,8 +601,8 @@ bool RISCVDAGToDAGISel::tryShrinkShlLogicImm(SDNode *Node) {
}

bool RISCVDAGToDAGISel::trySignedBitfieldExtract(SDNode *Node) {
// Only supported with XTHeadBb at the moment.
if (!Subtarget->hasVendorXTHeadBb())
// Only supported with XTHeadBb/XAndesPerf at the moment.
if (!Subtarget->hasVendorXTHeadBb() && !Subtarget->hasVendorXAndesPerf())
return false;

auto *N1C = dyn_cast<ConstantSDNode>(Node->getOperand(1));
Expand All @@ -615,7 +615,9 @@ bool RISCVDAGToDAGISel::trySignedBitfieldExtract(SDNode *Node) {

auto BitfieldExtract = [&](SDValue N0, unsigned Msb, unsigned Lsb, SDLoc DL,
MVT VT) {
return CurDAG->getMachineNode(RISCV::TH_EXT, DL, VT, N0.getOperand(0),
unsigned Opc =
Subtarget->hasVendorXTHeadBb() ? RISCV::TH_EXT : RISCV::NDS_BFOS;
return CurDAG->getMachineNode(Opc, DL, VT, N0.getOperand(0),
CurDAG->getTargetConstant(Msb, DL, VT),
CurDAG->getTargetConstant(Lsb, DL, VT));
};
Expand Down
32 changes: 32 additions & 0 deletions llvm/test/CodeGen/RISCV/rv32xandesperf.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -70,6 +70,38 @@ define i64 @bfoz_from_lshr_and_i64(i64 %x) {
ret i64 %shifted
}

define i32 @bfos_from_ashr_shl_i32(i32 %x) {
; CHECK-LABEL: bfos_from_ashr_shl_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfos a0, a0, 23, 16
; CHECK-NEXT: ret
%shl = shl i32 %x, 8
%ashr = ashr i32 %shl, 24
ret i32 %ashr
}

define i32 @bfos_from_ashr_sexti8_i32(i8 %x) {
; CHECK-LABEL: bfos_from_ashr_sexti8_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $x11 killed $x10
; CHECK-NEXT: nds.bfos a0, a0, 7, 5
; CHECK-NEXT: ret
%sext = sext i8 %x to i32
%ashr = ashr i32 %sext, 5
ret i32 %ashr
}

define i32 @bfos_from_ashr_sexti16_i32(i16 %x) {
; CHECK-LABEL: bfos_from_ashr_sexti16_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $x11 killed $x10
; CHECK-NEXT: nds.bfos a0, a0, 15, 11
; CHECK-NEXT: ret
%sext = sext i16 %x to i32
%ashr = ashr i32 %sext, 11
ret i32 %ashr
}

define i32 @sexti1_i32(i32 %a) {
; CHECK-LABEL: sexti1_i32:
; CHECK: # %bb.0:
Expand Down
60 changes: 60 additions & 0 deletions llvm/test/CodeGen/RISCV/rv64xandesperf.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -60,6 +60,66 @@ define i64 @bfoz_from_lshr_and_i64(i64 %x) {
ret i64 %shifted
}

define i32 @bfos_from_ashr_shl_i32(i32 %x) {
; CHECK-LABEL: bfos_from_ashr_shl_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfos a0, a0, 23, 16
; CHECK-NEXT: ret
%shl = shl i32 %x, 8
%ashr = ashr i32 %shl, 24
ret i32 %ashr
}

define i64 @bfos_from_ashr_shl_i64(i64 %x) {
; CHECK-LABEL: bfos_from_ashr_shl_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfos a0, a0, 55, 16
; CHECK-NEXT: ret
%shl = shl i64 %x, 8
%ashr = ashr i64 %shl, 24
ret i64 %ashr
}

define i32 @bfos_from_ashr_sexti8_i32(i8 %x) {
; CHECK-LABEL: bfos_from_ashr_sexti8_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfos a0, a0, 7, 5
; CHECK-NEXT: ret
%sext = sext i8 %x to i32
%ashr = ashr i32 %sext, 5
ret i32 %ashr
}

define i64 @bfos_from_ashr_sexti8_i64(i8 %x) {
; CHECK-LABEL: bfos_from_ashr_sexti8_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfos a0, a0, 7, 5
; CHECK-NEXT: ret
%sext = sext i8 %x to i64
%ashr = ashr i64 %sext, 5
ret i64 %ashr
}

define i32 @bfos_from_ashr_sexti16_i32(i16 %x) {
; CHECK-LABEL: bfos_from_ashr_sexti16_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfos a0, a0, 15, 11
; CHECK-NEXT: ret
%sext = sext i16 %x to i32
%ashr = ashr i32 %sext, 11
ret i32 %ashr
}

define i64 @bfos_from_ashr_sexti16_i64(i16 %x) {
; CHECK-LABEL: bfos_from_ashr_sexti16_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfos a0, a0, 15, 11
; CHECK-NEXT: ret
%sext = sext i16 %x to i64
%ashr = ashr i64 %sext, 11
ret i64 %ashr
}

define signext i32 @sexti1_i32(i32 signext %a) {
; CHECK-LABEL: sexti1_i32:
; CHECK: # %bb.0:
Expand Down
Loading