[VPlan] Simplify PredPHI LiveIn -> LiveIn #142271
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5f39be5 ([VPlan] Use InstSimplifyFolder instead of TargetFolder) updated simplifyRecipe to fold live-ins to Values that are not necessarily Constant, but forgot to update the corresponding PredPHI folder, which still folds PredPHI constant -> constant. Update it to fold PredPHI LiveIn -> LiveIn. Fixes llvm#141968.
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@llvm/pr-subscribers-llvm-transforms Author: Ramkumar Ramachandra (artagnon) Changes5f39be5 ([VPlan] Use InstSimplifyFolder instead of TargetFolder) updated simplifyRecipe to fold live-ins to Values that are not necessarily Constant, but forgot to update the corresponding PredPHI folder, which still folds PredPHI constant -> constant. Update it to fold PredPHI LiveIn -> LiveIn. Fixes #141968. Full diff: https://github.com/llvm/llvm-project/pull/142271.diff 2 Files Affected:
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index beab52fc3b133..8198e8705d6f5 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -1011,14 +1011,12 @@ static void simplifyRecipe(VPRecipeBase &R, VPTypeAnalysis &TypeInfo) {
.Default([](auto *) { return false; }))
return;
- // Fold PredPHI constant -> constant.
+ // Fold PredPHI LiveIn -> LiveIn.
if (auto *PredPHI = dyn_cast<VPPredInstPHIRecipe>(&R)) {
- VPlan *Plan = R.getParent()->getPlan();
VPValue *Op = PredPHI->getOperand(0);
if (!Op->isLiveIn() || !Op->getLiveInIRValue())
return;
- if (auto *C = dyn_cast<Constant>(Op->getLiveInIRValue()))
- PredPHI->replaceAllUsesWith(Plan->getOrAddLiveIn(C));
+ PredPHI->replaceAllUsesWith(Op);
}
// VPScalarIVSteps can only be simplified after unrolling. VPScalarIVSteps for
diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr141968-instsimplifyfolder.ll b/llvm/test/Transforms/LoopVectorize/X86/pr141968-instsimplifyfolder.ll
new file mode 100644
index 0000000000000..9a70ed451cf42
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/X86/pr141968-instsimplifyfolder.ll
@@ -0,0 +1,150 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
+; RUN: opt -passes=loop-vectorize -S %s | FileCheck %s
+
+target triple = "x86_64"
+
+define i8 @pr141968(i1 %cond, i8 %v) {
+; CHECK-LABEL: define i8 @pr141968(
+; CHECK-SAME: i1 [[COND:%.*]], i8 [[V:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[ZEXT_TRUE:%.*]] = zext i1 true to i16
+; CHECK-NEXT: [[SEXT:%.*]] = sext i8 [[V]] to i16
+; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i1> poison, i1 [[COND]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i1> [[BROADCAST_SPLATINSERT]], <16 x i1> poison, <16 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP0:%.*]] = xor <16 x i1> [[BROADCAST_SPLAT]], splat (i1 true)
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_SDIV_CONTINUE30:.*]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <16 x i1> [[TMP0]], i32 0
+; CHECK-NEXT: br i1 [[TMP1]], label %[[PRED_SDIV_IF:.*]], label %[[PRED_SDIV_CONTINUE:.*]]
+; CHECK: [[PRED_SDIV_IF]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE]]
+; CHECK: [[PRED_SDIV_CONTINUE]]:
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <16 x i1> [[TMP0]], i32 1
+; CHECK-NEXT: br i1 [[TMP2]], label %[[PRED_SDIV_IF1:.*]], label %[[PRED_SDIV_CONTINUE2:.*]]
+; CHECK: [[PRED_SDIV_IF1]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE2]]
+; CHECK: [[PRED_SDIV_CONTINUE2]]:
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <16 x i1> [[TMP0]], i32 2
+; CHECK-NEXT: br i1 [[TMP3]], label %[[PRED_SDIV_IF3:.*]], label %[[PRED_SDIV_CONTINUE4:.*]]
+; CHECK: [[PRED_SDIV_IF3]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE4]]
+; CHECK: [[PRED_SDIV_CONTINUE4]]:
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <16 x i1> [[TMP0]], i32 3
+; CHECK-NEXT: br i1 [[TMP4]], label %[[PRED_SDIV_IF5:.*]], label %[[PRED_SDIV_CONTINUE6:.*]]
+; CHECK: [[PRED_SDIV_IF5]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE6]]
+; CHECK: [[PRED_SDIV_CONTINUE6]]:
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <16 x i1> [[TMP0]], i32 4
+; CHECK-NEXT: br i1 [[TMP5]], label %[[PRED_SDIV_IF7:.*]], label %[[PRED_SDIV_CONTINUE8:.*]]
+; CHECK: [[PRED_SDIV_IF7]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE8]]
+; CHECK: [[PRED_SDIV_CONTINUE8]]:
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <16 x i1> [[TMP0]], i32 5
+; CHECK-NEXT: br i1 [[TMP6]], label %[[PRED_SDIV_IF9:.*]], label %[[PRED_SDIV_CONTINUE10:.*]]
+; CHECK: [[PRED_SDIV_IF9]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE10]]
+; CHECK: [[PRED_SDIV_CONTINUE10]]:
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <16 x i1> [[TMP0]], i32 6
+; CHECK-NEXT: br i1 [[TMP7]], label %[[PRED_SDIV_IF11:.*]], label %[[PRED_SDIV_CONTINUE12:.*]]
+; CHECK: [[PRED_SDIV_IF11]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE12]]
+; CHECK: [[PRED_SDIV_CONTINUE12]]:
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <16 x i1> [[TMP0]], i32 7
+; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_SDIV_IF13:.*]], label %[[PRED_SDIV_CONTINUE14:.*]]
+; CHECK: [[PRED_SDIV_IF13]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE14]]
+; CHECK: [[PRED_SDIV_CONTINUE14]]:
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <16 x i1> [[TMP0]], i32 8
+; CHECK-NEXT: br i1 [[TMP9]], label %[[PRED_SDIV_IF15:.*]], label %[[PRED_SDIV_CONTINUE16:.*]]
+; CHECK: [[PRED_SDIV_IF15]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE16]]
+; CHECK: [[PRED_SDIV_CONTINUE16]]:
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <16 x i1> [[TMP0]], i32 9
+; CHECK-NEXT: br i1 [[TMP10]], label %[[PRED_SDIV_IF17:.*]], label %[[PRED_SDIV_CONTINUE18:.*]]
+; CHECK: [[PRED_SDIV_IF17]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE18]]
+; CHECK: [[PRED_SDIV_CONTINUE18]]:
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <16 x i1> [[TMP0]], i32 10
+; CHECK-NEXT: br i1 [[TMP11]], label %[[PRED_SDIV_IF19:.*]], label %[[PRED_SDIV_CONTINUE20:.*]]
+; CHECK: [[PRED_SDIV_IF19]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE20]]
+; CHECK: [[PRED_SDIV_CONTINUE20]]:
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <16 x i1> [[TMP0]], i32 11
+; CHECK-NEXT: br i1 [[TMP12]], label %[[PRED_SDIV_IF21:.*]], label %[[PRED_SDIV_CONTINUE22:.*]]
+; CHECK: [[PRED_SDIV_IF21]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE22]]
+; CHECK: [[PRED_SDIV_CONTINUE22]]:
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <16 x i1> [[TMP0]], i32 12
+; CHECK-NEXT: br i1 [[TMP13]], label %[[PRED_SDIV_IF23:.*]], label %[[PRED_SDIV_CONTINUE24:.*]]
+; CHECK: [[PRED_SDIV_IF23]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE24]]
+; CHECK: [[PRED_SDIV_CONTINUE24]]:
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <16 x i1> [[TMP0]], i32 13
+; CHECK-NEXT: br i1 [[TMP14]], label %[[PRED_SDIV_IF25:.*]], label %[[PRED_SDIV_CONTINUE26:.*]]
+; CHECK: [[PRED_SDIV_IF25]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE26]]
+; CHECK: [[PRED_SDIV_CONTINUE26]]:
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <16 x i1> [[TMP0]], i32 14
+; CHECK-NEXT: br i1 [[TMP15]], label %[[PRED_SDIV_IF27:.*]], label %[[PRED_SDIV_CONTINUE28:.*]]
+; CHECK: [[PRED_SDIV_IF27]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE28]]
+; CHECK: [[PRED_SDIV_CONTINUE28]]:
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <16 x i1> [[TMP0]], i32 15
+; CHECK-NEXT: br i1 [[TMP16]], label %[[PRED_SDIV_IF29:.*]], label %[[PRED_SDIV_CONTINUE30]]
+; CHECK: [[PRED_SDIV_IF29]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE30]]
+; CHECK: [[PRED_SDIV_CONTINUE30]]:
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT31:%.*]] = insertelement <16 x i8> poison, i8 [[V]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT32:%.*]] = shufflevector <16 x i8> [[BROADCAST_SPLATINSERT31]], <16 x i8> poison, <16 x i32> zeroinitializer
+; CHECK-NEXT: [[PREDPHI:%.*]] = select <16 x i1> [[BROADCAST_SPLAT]], <16 x i8> zeroinitializer, <16 x i8> [[BROADCAST_SPLAT32]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16
+; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[INDEX_NEXT]], 256
+; CHECK-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[TMP18:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 15
+; CHECK-NEXT: br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i8 [ 0, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
+; CHECK: [[LOOP_HEADER]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i8 [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
+; CHECK-NEXT: br i1 [[COND]], label %[[LOOP_LATCH]], label %[[COND_FALSE:.*]]
+; CHECK: [[COND_FALSE]]:
+; CHECK-NEXT: [[SDIV:%.*]] = sdiv i16 [[SEXT]], [[ZEXT_TRUE]]
+; CHECK-NEXT: [[SDIV_TRUNC:%.*]] = trunc i16 [[SDIV]] to i8
+; CHECK-NEXT: br label %[[LOOP_LATCH]]
+; CHECK: [[LOOP_LATCH]]:
+; CHECK-NEXT: [[RET:%.*]] = phi i8 [ [[SDIV_TRUNC]], %[[COND_FALSE]] ], [ 0, %[[LOOP_HEADER]] ]
+; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i8 [[IV_NEXT]], 0
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[RET_LCSSA:%.*]] = phi i8 [ [[RET]], %[[LOOP_LATCH]] ], [ [[TMP18]], %[[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: ret i8 [[RET_LCSSA]]
+;
+entry:
+ %zext.true = zext i1 true to i16
+ %sext = sext i8 %v to i16
+ br label %loop.header
+
+loop.header: ; preds = %loop.latch, %entry
+ %iv = phi i8 [ %iv.next, %loop.latch ], [ 0, %entry ]
+ br i1 %cond, label %loop.latch, label %cond.false
+
+cond.false: ; preds = %loop.header
+ %sdiv = sdiv i16 %sext, %zext.true
+ %sdiv.trunc = trunc i16 %sdiv to i8
+ br label %loop.latch
+
+loop.latch: ; preds = %cond.false, %loop.header
+ %ret = phi i8 [ %sdiv.trunc, %cond.false ], [ 0, %loop.header ]
+ %iv.next = add i8 %iv, 1
+ %exitcond = icmp eq i8 %iv.next, 0
+ br i1 %exitcond, label %exit, label %loop.header
+
+exit: ; preds = %loop.latch
+ ret i8 %ret
+}
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@llvm/pr-subscribers-vectorizers Author: Ramkumar Ramachandra (artagnon) Changes5f39be5 ([VPlan] Use InstSimplifyFolder instead of TargetFolder) updated simplifyRecipe to fold live-ins to Values that are not necessarily Constant, but forgot to update the corresponding PredPHI folder, which still folds PredPHI constant -> constant. Update it to fold PredPHI LiveIn -> LiveIn. Fixes #141968. Full diff: https://github.com/llvm/llvm-project/pull/142271.diff 2 Files Affected:
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index beab52fc3b133..8198e8705d6f5 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -1011,14 +1011,12 @@ static void simplifyRecipe(VPRecipeBase &R, VPTypeAnalysis &TypeInfo) {
.Default([](auto *) { return false; }))
return;
- // Fold PredPHI constant -> constant.
+ // Fold PredPHI LiveIn -> LiveIn.
if (auto *PredPHI = dyn_cast<VPPredInstPHIRecipe>(&R)) {
- VPlan *Plan = R.getParent()->getPlan();
VPValue *Op = PredPHI->getOperand(0);
if (!Op->isLiveIn() || !Op->getLiveInIRValue())
return;
- if (auto *C = dyn_cast<Constant>(Op->getLiveInIRValue()))
- PredPHI->replaceAllUsesWith(Plan->getOrAddLiveIn(C));
+ PredPHI->replaceAllUsesWith(Op);
}
// VPScalarIVSteps can only be simplified after unrolling. VPScalarIVSteps for
diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr141968-instsimplifyfolder.ll b/llvm/test/Transforms/LoopVectorize/X86/pr141968-instsimplifyfolder.ll
new file mode 100644
index 0000000000000..9a70ed451cf42
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/X86/pr141968-instsimplifyfolder.ll
@@ -0,0 +1,150 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
+; RUN: opt -passes=loop-vectorize -S %s | FileCheck %s
+
+target triple = "x86_64"
+
+define i8 @pr141968(i1 %cond, i8 %v) {
+; CHECK-LABEL: define i8 @pr141968(
+; CHECK-SAME: i1 [[COND:%.*]], i8 [[V:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[ZEXT_TRUE:%.*]] = zext i1 true to i16
+; CHECK-NEXT: [[SEXT:%.*]] = sext i8 [[V]] to i16
+; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i1> poison, i1 [[COND]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i1> [[BROADCAST_SPLATINSERT]], <16 x i1> poison, <16 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP0:%.*]] = xor <16 x i1> [[BROADCAST_SPLAT]], splat (i1 true)
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_SDIV_CONTINUE30:.*]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <16 x i1> [[TMP0]], i32 0
+; CHECK-NEXT: br i1 [[TMP1]], label %[[PRED_SDIV_IF:.*]], label %[[PRED_SDIV_CONTINUE:.*]]
+; CHECK: [[PRED_SDIV_IF]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE]]
+; CHECK: [[PRED_SDIV_CONTINUE]]:
+; CHECK-NEXT: [[TMP2:%.*]] = extractelement <16 x i1> [[TMP0]], i32 1
+; CHECK-NEXT: br i1 [[TMP2]], label %[[PRED_SDIV_IF1:.*]], label %[[PRED_SDIV_CONTINUE2:.*]]
+; CHECK: [[PRED_SDIV_IF1]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE2]]
+; CHECK: [[PRED_SDIV_CONTINUE2]]:
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <16 x i1> [[TMP0]], i32 2
+; CHECK-NEXT: br i1 [[TMP3]], label %[[PRED_SDIV_IF3:.*]], label %[[PRED_SDIV_CONTINUE4:.*]]
+; CHECK: [[PRED_SDIV_IF3]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE4]]
+; CHECK: [[PRED_SDIV_CONTINUE4]]:
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <16 x i1> [[TMP0]], i32 3
+; CHECK-NEXT: br i1 [[TMP4]], label %[[PRED_SDIV_IF5:.*]], label %[[PRED_SDIV_CONTINUE6:.*]]
+; CHECK: [[PRED_SDIV_IF5]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE6]]
+; CHECK: [[PRED_SDIV_CONTINUE6]]:
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <16 x i1> [[TMP0]], i32 4
+; CHECK-NEXT: br i1 [[TMP5]], label %[[PRED_SDIV_IF7:.*]], label %[[PRED_SDIV_CONTINUE8:.*]]
+; CHECK: [[PRED_SDIV_IF7]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE8]]
+; CHECK: [[PRED_SDIV_CONTINUE8]]:
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <16 x i1> [[TMP0]], i32 5
+; CHECK-NEXT: br i1 [[TMP6]], label %[[PRED_SDIV_IF9:.*]], label %[[PRED_SDIV_CONTINUE10:.*]]
+; CHECK: [[PRED_SDIV_IF9]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE10]]
+; CHECK: [[PRED_SDIV_CONTINUE10]]:
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <16 x i1> [[TMP0]], i32 6
+; CHECK-NEXT: br i1 [[TMP7]], label %[[PRED_SDIV_IF11:.*]], label %[[PRED_SDIV_CONTINUE12:.*]]
+; CHECK: [[PRED_SDIV_IF11]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE12]]
+; CHECK: [[PRED_SDIV_CONTINUE12]]:
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <16 x i1> [[TMP0]], i32 7
+; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_SDIV_IF13:.*]], label %[[PRED_SDIV_CONTINUE14:.*]]
+; CHECK: [[PRED_SDIV_IF13]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE14]]
+; CHECK: [[PRED_SDIV_CONTINUE14]]:
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <16 x i1> [[TMP0]], i32 8
+; CHECK-NEXT: br i1 [[TMP9]], label %[[PRED_SDIV_IF15:.*]], label %[[PRED_SDIV_CONTINUE16:.*]]
+; CHECK: [[PRED_SDIV_IF15]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE16]]
+; CHECK: [[PRED_SDIV_CONTINUE16]]:
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <16 x i1> [[TMP0]], i32 9
+; CHECK-NEXT: br i1 [[TMP10]], label %[[PRED_SDIV_IF17:.*]], label %[[PRED_SDIV_CONTINUE18:.*]]
+; CHECK: [[PRED_SDIV_IF17]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE18]]
+; CHECK: [[PRED_SDIV_CONTINUE18]]:
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <16 x i1> [[TMP0]], i32 10
+; CHECK-NEXT: br i1 [[TMP11]], label %[[PRED_SDIV_IF19:.*]], label %[[PRED_SDIV_CONTINUE20:.*]]
+; CHECK: [[PRED_SDIV_IF19]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE20]]
+; CHECK: [[PRED_SDIV_CONTINUE20]]:
+; CHECK-NEXT: [[TMP12:%.*]] = extractelement <16 x i1> [[TMP0]], i32 11
+; CHECK-NEXT: br i1 [[TMP12]], label %[[PRED_SDIV_IF21:.*]], label %[[PRED_SDIV_CONTINUE22:.*]]
+; CHECK: [[PRED_SDIV_IF21]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE22]]
+; CHECK: [[PRED_SDIV_CONTINUE22]]:
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <16 x i1> [[TMP0]], i32 12
+; CHECK-NEXT: br i1 [[TMP13]], label %[[PRED_SDIV_IF23:.*]], label %[[PRED_SDIV_CONTINUE24:.*]]
+; CHECK: [[PRED_SDIV_IF23]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE24]]
+; CHECK: [[PRED_SDIV_CONTINUE24]]:
+; CHECK-NEXT: [[TMP14:%.*]] = extractelement <16 x i1> [[TMP0]], i32 13
+; CHECK-NEXT: br i1 [[TMP14]], label %[[PRED_SDIV_IF25:.*]], label %[[PRED_SDIV_CONTINUE26:.*]]
+; CHECK: [[PRED_SDIV_IF25]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE26]]
+; CHECK: [[PRED_SDIV_CONTINUE26]]:
+; CHECK-NEXT: [[TMP15:%.*]] = extractelement <16 x i1> [[TMP0]], i32 14
+; CHECK-NEXT: br i1 [[TMP15]], label %[[PRED_SDIV_IF27:.*]], label %[[PRED_SDIV_CONTINUE28:.*]]
+; CHECK: [[PRED_SDIV_IF27]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE28]]
+; CHECK: [[PRED_SDIV_CONTINUE28]]:
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <16 x i1> [[TMP0]], i32 15
+; CHECK-NEXT: br i1 [[TMP16]], label %[[PRED_SDIV_IF29:.*]], label %[[PRED_SDIV_CONTINUE30]]
+; CHECK: [[PRED_SDIV_IF29]]:
+; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE30]]
+; CHECK: [[PRED_SDIV_CONTINUE30]]:
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT31:%.*]] = insertelement <16 x i8> poison, i8 [[V]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT32:%.*]] = shufflevector <16 x i8> [[BROADCAST_SPLATINSERT31]], <16 x i8> poison, <16 x i32> zeroinitializer
+; CHECK-NEXT: [[PREDPHI:%.*]] = select <16 x i1> [[BROADCAST_SPLAT]], <16 x i8> zeroinitializer, <16 x i8> [[BROADCAST_SPLAT32]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16
+; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[INDEX_NEXT]], 256
+; CHECK-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[TMP18:%.*]] = extractelement <16 x i8> [[PREDPHI]], i32 15
+; CHECK-NEXT: br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i8 [ 0, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
+; CHECK: [[LOOP_HEADER]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i8 [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
+; CHECK-NEXT: br i1 [[COND]], label %[[LOOP_LATCH]], label %[[COND_FALSE:.*]]
+; CHECK: [[COND_FALSE]]:
+; CHECK-NEXT: [[SDIV:%.*]] = sdiv i16 [[SEXT]], [[ZEXT_TRUE]]
+; CHECK-NEXT: [[SDIV_TRUNC:%.*]] = trunc i16 [[SDIV]] to i8
+; CHECK-NEXT: br label %[[LOOP_LATCH]]
+; CHECK: [[LOOP_LATCH]]:
+; CHECK-NEXT: [[RET:%.*]] = phi i8 [ [[SDIV_TRUNC]], %[[COND_FALSE]] ], [ 0, %[[LOOP_HEADER]] ]
+; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i8 [[IV_NEXT]], 0
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[RET_LCSSA:%.*]] = phi i8 [ [[RET]], %[[LOOP_LATCH]] ], [ [[TMP18]], %[[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: ret i8 [[RET_LCSSA]]
+;
+entry:
+ %zext.true = zext i1 true to i16
+ %sext = sext i8 %v to i16
+ br label %loop.header
+
+loop.header: ; preds = %loop.latch, %entry
+ %iv = phi i8 [ %iv.next, %loop.latch ], [ 0, %entry ]
+ br i1 %cond, label %loop.latch, label %cond.false
+
+cond.false: ; preds = %loop.header
+ %sdiv = sdiv i16 %sext, %zext.true
+ %sdiv.trunc = trunc i16 %sdiv to i8
+ br label %loop.latch
+
+loop.latch: ; preds = %cond.false, %loop.header
+ %ret = phi i8 [ %sdiv.trunc, %cond.false ], [ 0, %loop.header ]
+ %iv.next = add i8 %iv, 1
+ %exitcond = icmp eq i8 %iv.next, 0
+ br i1 %exitcond, label %exit, label %loop.header
+
+exit: ; preds = %loop.latch
+ ret i8 %ret
+}
|
fhahn
reviewed
Jun 1, 2025
sallto
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to sallto/llvm-project
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Jun 3, 2025
5f39be5 ([VPlan] Use InstSimplifyFolder instead of TargetFolder) updated simplifyRecipe to fold live-ins to Values that are not necessarily Constant, but forgot to update the corresponding PredPHI folder, which still folds PredPHI constant -> constant. Update it to fold PredPHI LiveIn -> LiveIn. Fixes llvm#141968.
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5f39be5 ([VPlan] Use InstSimplifyFolder instead of TargetFolder) updated simplifyRecipe to fold live-ins to Values that are not necessarily Constant, but forgot to update the corresponding PredPHI folder, which still folds PredPHI constant -> constant. Update it to fold PredPHI LiveIn -> LiveIn.
Fixes #141968.