Skip to content

[Codegen] Remove redundant instruction using machinelateCleanup #139716

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 11 commits into
base: main
Choose a base branch
from
Open

[Codegen] Remove redundant instruction using machinelateCleanup #139716

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
11 commits
Select commit Hold shift + click to select a range
214caf4
Remove redundant pseudo mov instruction
May 13, 2025
9a1de88
Remove the isPseudo check
May 13, 2025
71abb2b
Merge branch 'RemovePseudoMov' of github.com:rohitaggarwal007/llvm-pr…
May 13, 2025
2ab66a2
Fix the test cases
May 13, 2025
9ca3190
Update the logic for defs
May 15, 2025
33373fa
Restructure the if else ladder
May 15, 2025
b358511
Merge branch 'llvm:main' into RemovePseudoMov
rohitaggarwal007 May 16, 2025
a709a64
Cleanup test case and pass TRI as argument in isCandidate function
May 19, 2025
f7792d2
Updating the comments and isSubRegister call
May 19, 2025
3e1c49d
Merge branch 'llvm:main' into RemovePseudoMov
rohitaggarwal007 May 19, 2025
fe8860a
Merge branch 'llvm:main' into RemovePseudoMov
rohitaggarwal007 May 21, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
23 changes: 20 additions & 3 deletions llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -178,7 +178,7 @@ void MachineLateInstrsCleanup::removeRedundantDef(MachineInstr *MI) {
// and the only reg it may use is FrameReg. Typically this is an immediate
// load or a load-address instruction.
static bool isCandidate(const MachineInstr *MI, Register &DefedReg,
Register FrameReg) {
Register FrameReg, const TargetRegisterInfo *TRI) {
DefedReg = MCRegister::NoRegister;
bool SawStore = true;
if (!MI->isSafeToMove(SawStore) || MI->isImplicitDef() || MI->isInlineAsm())
Expand All @@ -187,9 +187,26 @@ static bool isCandidate(const MachineInstr *MI, Register &DefedReg,
const MachineOperand &MO = MI->getOperand(i);
if (MO.isReg()) {
if (MO.isDef()) {
// To get the \DefedReg value, we need to check that 1st MachineOperand
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This isnt' a /// comment, so the doxygen \ syntax won't do anything; plus I don't think it does anything for comments in the body of a function, only on the declaration

// is not dead and not implicit def.
// For example:
// renamable $r9d = MOV32r0 implicit-def dead $eflags, implicit-def $r9
// First operand is $r9d and it is not implicit def and not dead, So
// it is valid and we can use it in \DefedReg.
if (i == 0 && !MO.isImplicit() && !MO.isDead())
DefedReg = MO.getReg();
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I'd appreciate some comments to explain what's going on, for the existing cases and the new cases. Example:
// If the first def is explicit and not dead, remember it.
I'm not sure why explicit matters here.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Sure

else
// If DefedReg has a valid register, check the other operands
else if (DefedReg != MCRegister::NoRegister) {
// If the machineOperand is Dead and Implicit then continue
// to next operand.
if (MO.isDead() && MO.isImplicit())
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Example:
// If a later def is dead and implicit, ignore it.
Again I'm not sure why implicit matters.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Machine operand has this attribute for which I am trying do the enable the optimization.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Implicit doesn't have any semantic meaning though; in general a generic pass shouldn't need to be aware of whether the operand is implicit or not. If it's implicit it's there for liveness tracking and you can't ignore it

continue;
// If the machineOperand is Implicit and alias with DefedReg then
// continue to next operand.
if (MO.isImplicit() && TRI->isSubRegister(MO.getReg(), DefedReg))
continue;
return false;
} else
return false;
} else if (MO.getReg() && MO.getReg() != FrameReg)
return false;
Expand Down Expand Up @@ -235,7 +252,7 @@ bool MachineLateInstrsCleanup::processBlock(MachineBasicBlock *MBB) {
}

Register DefedReg;
bool IsCandidate = isCandidate(&MI, DefedReg, FrameReg);
bool IsCandidate = isCandidate(&MI, DefedReg, FrameReg, TRI);

// Check for an earlier identical and reusable instruction.
if (IsCandidate && MBBDefs.hasIdentical(DefedReg, &MI)) {
Expand Down
1 change: 0 additions & 1 deletion llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,6 @@ define void @widget(i32 %arg, i32 %arg1, ptr %arg2, ptr %arg3, ptr %arg4, i32 %a
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: mov x1, xzr
; CHECK-NEXT: mov w8, #1 ; =0x1
; CHECK-NEXT: stp xzr, xzr, [sp]
; CHECK-NEXT: stp x8, xzr, [sp, #16]
; CHECK-NEXT: bl _fprintf
Expand Down
1 change: 0 additions & 1 deletion llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -246,7 +246,6 @@ define void @call_with_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
; GFX8-ARCH-FLAT-NEXT: v_readlane_b32 s30, v3, 0
; GFX8-ARCH-FLAT-NEXT: s_mov_b32 s32, s33
; GFX8-ARCH-FLAT-NEXT: s_xor_saveexec_b64 s[0:1], -1
; GFX8-ARCH-FLAT-NEXT: s_add_i32 s3, s33, 8
; GFX8-ARCH-FLAT-NEXT: scratch_load_dword v3, off, s3 ; 4-byte Folded Reload
; GFX8-ARCH-FLAT-NEXT: s_mov_b64 exec, s[0:1]
; GFX8-ARCH-FLAT-NEXT: s_mov_b32 s33, s2
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -113,8 +113,7 @@ define amdgpu_kernel void @stored_fi_to_fi() #0 {

; GCN-LABEL: {{^}}stored_fi_to_global:
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
; GCN: buffer_store_dword [[FI]]
Comment on lines -116 to -117
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This lost the point of the test?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I will check

; GCN: buffer_store_dword v{{[0-9]+}}
define amdgpu_kernel void @stored_fi_to_global(ptr addrspace(1) %ptr) #0 {
%tmp = alloca float, addrspace(5)
store float 0.0, ptr addrspace(5) %tmp
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -72,8 +72,7 @@ done:
; GCN-LABEL: {{^}}test_sink_global_small_max_mubuf_offset:
; GCN: s_and_saveexec_b64
; SICIVI: buffer_load_sbyte {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4095{{$}}
; GFX9: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
; GFX9: global_load_sbyte {{v[0-9]+}}, [[ZERO]], {{s\[[0-9]+:[0-9]+\]}} offset:4095{{$}}
; GFX9: global_load_sbyte {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} offset:4095{{$}}
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This still needs the zero check, the mov is just above here now?

; GCN: {{^}}.LBB2_2:
; GCN: s_or_b64 exec
define amdgpu_kernel void @test_sink_global_small_max_mubuf_offset(ptr addrspace(1) %out, ptr addrspace(1) %in) {
Expand Down
51 changes: 0 additions & 51 deletions llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
View file
Open in desktop

Large diffs are not rendered by default.

5 changes: 0 additions & 5 deletions llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -125,7 +125,6 @@ define void @test_sgpr_offset_function_scavenge_fail_func() #2 {
; MUBUF-NEXT: ;;#ASMEND
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ;;#ASMEND
; MUBUF-NEXT: s_add_i32 s10, s32, 0x40100
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s10 ; 4-byte Folded Reload
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: ;;#ASMSTART
Expand All @@ -147,7 +146,6 @@ define void @test_sgpr_offset_function_scavenge_fail_func() #2 {
; FLATSCR-NEXT: ;;#ASMEND
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ;;#ASMEND
; FLATSCR-NEXT: s_add_i32 s8, s32, 0x1004
; FLATSCR-NEXT: scratch_load_dword v0, off, s8 ; 4-byte Folded Reload
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: ;;#ASMSTART
Expand Down Expand Up @@ -466,7 +464,6 @@ define void @test_sgpr_offset_function() {
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill
; MUBUF-NEXT: ;;#ASMSTART
; MUBUF-NEXT: ;;#ASMEND
; MUBUF-NEXT: s_add_i32 s4, s32, 0x40100
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8
Expand All @@ -482,7 +479,6 @@ define void @test_sgpr_offset_function() {
; FLATSCR-NEXT: scratch_store_dword off, v0, s0 ; 4-byte Folded Spill
; FLATSCR-NEXT: ;;#ASMSTART
; FLATSCR-NEXT: ;;#ASMEND
; FLATSCR-NEXT: s_add_i32 s0, s32, 0x1004
; FLATSCR-NEXT: scratch_load_dword v0, off, s0 ; 4-byte Folded Reload
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: scratch_store_dword off, v0, s32 offset:8
Expand Down Expand Up @@ -586,7 +582,6 @@ define void @test_inst_offset_subregs_function() {
; MUBUF-NEXT: ;;#ASMEND
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:8 glc
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_add_i32 s4, s32, 0x3ff00
; MUBUF-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload
; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s4 offset:4 ; 4-byte Folded Reload
; MUBUF-NEXT: s_waitcnt vmcnt(0)
Expand Down
1 change: 0 additions & 1 deletion llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,6 @@ define fastcc void @mp_sqrt(i32 %n, i32 %radix, ptr %in, ptr %out, ptr %tmp1, pt
; CHECK-NEXT: andl $1, %ebp
; CHECK-NEXT: xorpd %xmm0, %xmm0
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: xorpd %xmm1, %xmm1
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_7: # %bb.i28.i
Expand Down
2 changes: 0 additions & 2 deletions llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -174,7 +174,6 @@ define dso_local void @test4(i16 signext %0, i16 signext %1) nounwind {
; CHECK-NEXT: incl %edi
; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB3_4
; CHECK-NEXT: .LBB3_2: # %amx2
Expand All @@ -190,7 +189,6 @@ define dso_local void @test4(i16 signext %0, i16 signext %1) nounwind {
; CHECK-NEXT: decl %edi
; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB3_2
; CHECK-NEXT: .LBB3_4: # %amx1
Expand Down
1 change: 0 additions & 1 deletion llvm/test/CodeGen/X86/avx-load-store.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -216,7 +216,6 @@ define void @f_f() nounwind {
; CHECK-NEXT: jne .LBB9_2
; CHECK-NEXT: # %bb.1: # %cif_mask_all
; CHECK-NEXT: .LBB9_2: # %cif_mask_mixed
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB9_4
; CHECK-NEXT: # %bb.3: # %cif_mixed_test_all
Expand Down
17 changes: 6 additions & 11 deletions llvm/test/CodeGen/X86/isel-brcond-fcmp.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -533,12 +533,10 @@ define i32 @fcmp_ogt1(float %x) {
; SDAG-X64: ## %bb.0:
; SDAG-X64-NEXT: xorl %eax, %eax
; SDAG-X64-NEXT: testb %al, %al
; SDAG-X64-NEXT: je LBB16_1
; SDAG-X64-NEXT: ## %bb.2: ## %bb1
; SDAG-X64-NEXT: xorl %eax, %eax
; SDAG-X64-NEXT: retq
; SDAG-X64-NEXT: LBB16_1: ## %bb2
; SDAG-X64-NEXT: jne LBB16_2
; SDAG-X64-NEXT: ## %bb.1: ## %bb2
; SDAG-X64-NEXT: movl $1, %eax
; SDAG-X64-NEXT: LBB16_2: ## %bb1
; SDAG-X64-NEXT: retq
;
; FASTISEL-X64-LABEL: fcmp_ogt1:
Expand Down Expand Up @@ -671,12 +669,10 @@ define i32 @fcmp_olt1(float %x) {
; SDAG-X64: ## %bb.0:
; SDAG-X64-NEXT: xorl %eax, %eax
; SDAG-X64-NEXT: testb %al, %al
; SDAG-X64-NEXT: je LBB20_1
; SDAG-X64-NEXT: ## %bb.2: ## %bb1
; SDAG-X64-NEXT: xorl %eax, %eax
; SDAG-X64-NEXT: retq
; SDAG-X64-NEXT: LBB20_1: ## %bb2
; SDAG-X64-NEXT: jne LBB20_2
; SDAG-X64-NEXT: ## %bb.1: ## %bb2
; SDAG-X64-NEXT: movl $1, %eax
; SDAG-X64-NEXT: LBB20_2: ## %bb1
; SDAG-X64-NEXT: retq
;
; FASTISEL-X64-LABEL: fcmp_olt1:
Expand Down Expand Up @@ -811,7 +807,6 @@ define i32 @fcmp_one1(float %x) {
; SDAG-X64-NEXT: testb %al, %al
; SDAG-X64-NEXT: je LBB24_1
; SDAG-X64-NEXT: ## %bb.2: ## %bb1
; SDAG-X64-NEXT: xorl %eax, %eax
; SDAG-X64-NEXT: retq
; SDAG-X64-NEXT: LBB24_1: ## %bb2
; SDAG-X64-NEXT: movl $1, %eax
Expand Down
40 changes: 15 additions & 25 deletions llvm/test/CodeGen/X86/isel-brcond-icmp.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -763,12 +763,10 @@ define i32 @icmp_ne(i32 %x) {
; SDAG: ## %bb.0:
; SDAG-NEXT: xorl %eax, %eax
; SDAG-NEXT: testb %al, %al
; SDAG-NEXT: je LBB11_1
; SDAG-NEXT: ## %bb.2: ## %bb1
; SDAG-NEXT: xorl %eax, %eax
; SDAG-NEXT: ret{{[l|q]}}
; SDAG-NEXT: LBB11_1: ## %bb2
; SDAG-NEXT: jne LBB11_2
; SDAG-NEXT: ## %bb.1: ## %bb2
; SDAG-NEXT: movl $1, %eax
; SDAG-NEXT: LBB11_2: ## %bb1
; SDAG-NEXT: ret{{[l|q]}}
;
; FASTISEL-LABEL: icmp_ne:
Expand Down Expand Up @@ -815,12 +813,10 @@ define i32 @icmp_ugt(i32 %x) {
; SDAG: ## %bb.0:
; SDAG-NEXT: xorl %eax, %eax
; SDAG-NEXT: testb %al, %al
; SDAG-NEXT: je LBB12_1
; SDAG-NEXT: ## %bb.2: ## %bb1
; SDAG-NEXT: xorl %eax, %eax
; SDAG-NEXT: ret{{[l|q]}}
; SDAG-NEXT: LBB12_1: ## %bb2
; SDAG-NEXT: jne LBB12_2
; SDAG-NEXT: ## %bb.1: ## %bb2
; SDAG-NEXT: movl $1, %eax
; SDAG-NEXT: LBB12_2: ## %bb1
; SDAG-NEXT: ret{{[l|q]}}
;
; FASTISEL-LABEL: icmp_ugt:
Expand Down Expand Up @@ -919,12 +915,10 @@ define i32 @icmp_ult(i32 %x) {
; SDAG: ## %bb.0:
; SDAG-NEXT: xorl %eax, %eax
; SDAG-NEXT: testb %al, %al
; SDAG-NEXT: je LBB14_1
; SDAG-NEXT: ## %bb.2: ## %bb1
; SDAG-NEXT: xorl %eax, %eax
; SDAG-NEXT: ret{{[l|q]}}
; SDAG-NEXT: LBB14_1: ## %bb2
; SDAG-NEXT: jne LBB14_2
; SDAG-NEXT: ## %bb.1: ## %bb2
; SDAG-NEXT: movl $1, %eax
; SDAG-NEXT: LBB14_2: ## %bb1
; SDAG-NEXT: ret{{[l|q]}}
;
; FASTISEL-LABEL: icmp_ult:
Expand Down Expand Up @@ -1023,12 +1017,10 @@ define i32 @icmp_sgt(i32 %x) {
; SDAG: ## %bb.0:
; SDAG-NEXT: xorl %eax, %eax
; SDAG-NEXT: testb %al, %al
; SDAG-NEXT: je LBB16_1
; SDAG-NEXT: ## %bb.2: ## %bb1
; SDAG-NEXT: xorl %eax, %eax
; SDAG-NEXT: ret{{[l|q]}}
; SDAG-NEXT: LBB16_1: ## %bb2
; SDAG-NEXT: jne LBB16_2
; SDAG-NEXT: ## %bb.1: ## %bb2
; SDAG-NEXT: movl $1, %eax
; SDAG-NEXT: LBB16_2: ## %bb1
; SDAG-NEXT: ret{{[l|q]}}
;
; FASTISEL-LABEL: icmp_sgt:
Expand Down Expand Up @@ -1127,12 +1119,10 @@ define i32 @icmp_slt(i32 %x) {
; SDAG: ## %bb.0:
; SDAG-NEXT: xorl %eax, %eax
; SDAG-NEXT: testb %al, %al
; SDAG-NEXT: je LBB18_1
; SDAG-NEXT: ## %bb.2: ## %bb1
; SDAG-NEXT: xorl %eax, %eax
; SDAG-NEXT: ret{{[l|q]}}
; SDAG-NEXT: LBB18_1: ## %bb2
; SDAG-NEXT: jne LBB18_2
; SDAG-NEXT: ## %bb.1: ## %bb2
; SDAG-NEXT: movl $1, %eax
; SDAG-NEXT: LBB18_2: ## %bb1
; SDAG-NEXT: ret{{[l|q]}}
;
; FASTISEL-LABEL: icmp_slt:
Expand Down
1 change: 0 additions & 1 deletion llvm/test/CodeGen/X86/pr36602.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@ define i32 @fn2() {
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB0_2: # %bb2
; CHECK-NEXT: movl $1, %eax
Expand Down
1 change: 0 additions & 1 deletion llvm/test/CodeGen/X86/pr38795.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -128,7 +128,6 @@ define dso_local void @fn() {
; CHECK-NEXT: jne .LBB0_15
; CHECK-NEXT: # %bb.14: # %if.then31
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: xorl %ebp, %ebp
; CHECK-NEXT: jmp .LBB0_15
; CHECK-NEXT: .p2align 4
Expand Down
1 change: 0 additions & 1 deletion llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -288,7 +288,6 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je LBB0_54
; CHECK-NEXT: ## %bb.50: ## %for.body1664.lr.ph
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r14 ## 8-byte Reload
; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ebp ## 4-byte Reload
Expand Down
4 changes: 0 additions & 4 deletions llvm/test/CodeGen/X86/scheduler-backtracking.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -754,7 +754,6 @@ define i256 @PR25498(i256 %a) nounwind {
; ILP-NEXT: testq %r11, %r11
; ILP-NEXT: cmovneq %rdx, %rcx
; ILP-NEXT: orq $128, %rcx
; ILP-NEXT: xorl %edi, %edi
; ILP-NEXT: orq %r10, %r9
; ILP-NEXT: cmovneq %rsi, %rcx
; ILP-NEXT: jmp .LBB4_3
Expand Down Expand Up @@ -803,7 +802,6 @@ define i256 @PR25498(i256 %a) nounwind {
; HYBRID-NEXT: orq $128, %rcx
; HYBRID-NEXT: orq %r10, %r9
; HYBRID-NEXT: cmovneq %rdx, %rcx
; HYBRID-NEXT: xorl %edi, %edi
; HYBRID-NEXT: jmp .LBB4_3
; HYBRID-NEXT: .LBB4_1:
; HYBRID-NEXT: movl $256, %ecx # imm = 0x100
Expand Down Expand Up @@ -850,7 +848,6 @@ define i256 @PR25498(i256 %a) nounwind {
; BURR-NEXT: orq $128, %rcx
; BURR-NEXT: orq %r10, %r9
; BURR-NEXT: cmovneq %rdx, %rcx
; BURR-NEXT: xorl %edi, %edi
; BURR-NEXT: jmp .LBB4_3
; BURR-NEXT: .LBB4_1:
; BURR-NEXT: movl $256, %ecx # imm = 0x100
Expand Down Expand Up @@ -897,7 +894,6 @@ define i256 @PR25498(i256 %a) nounwind {
; SRC-NEXT: orq $128, %rcx
; SRC-NEXT: orq %r10, %r9
; SRC-NEXT: cmovneq %rdx, %rcx
; SRC-NEXT: xorl %edi, %edi
; SRC-NEXT: jmp .LBB4_3
; SRC-NEXT: .LBB4_1:
; SRC-NEXT: movl $256, %ecx # imm = 0x100
Expand Down
5 changes: 0 additions & 5 deletions llvm/test/CodeGen/X86/tail-opts.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -245,11 +245,9 @@ define fastcc void @c_expand_expr_stmt(ptr %expr) nounwind {
; CHECK-NEXT: jne .LBB3_9
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: movzbl 0, %ebx
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB3_8
; CHECK-NEXT: # %bb.2: # %bb.i
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je .LBB3_8
; CHECK-NEXT: # %bb.3: # %lvalue_p.exit
Expand Down Expand Up @@ -519,7 +517,6 @@ define dso_local void @two() nounwind optsize {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je .LBB7_1
; CHECK-NEXT: # %bb.2: # %return
Expand Down Expand Up @@ -560,7 +557,6 @@ define dso_local void @two_pgso() nounwind !prof !14 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je .LBB8_1
; CHECK-NEXT: # %bb.2: # %return
Expand Down Expand Up @@ -603,7 +599,6 @@ define dso_local void @two_minsize() nounwind minsize {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je .LBB9_1
; CHECK-NEXT: # %bb.2: # %return
Expand Down
6 changes: 1 addition & 5 deletions llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -270,11 +270,7 @@ define i64 @PR55050() {
; X86: # %bb.0: # %entry
; X86-NEXT: xorl %eax, %eax
; X86-NEXT: testb %al, %al
; X86-NEXT: jne .LBB15_2
; X86-NEXT: # %bb.1: # %if
; X86-NEXT: xorl %eax, %eax
; X86-NEXT: .LBB15_2: # %exit
; X86-NEXT: movl %eax, %edx
; X86-NEXT: movl %eax, %edx
; X86-NEXT: retl
;
; X64-LABEL: PR55050:
Expand Down
2 changes: 0 additions & 2 deletions llvm/test/CodeGen/X86/x86-cmov-converter.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -365,7 +365,6 @@ define i32 @MaxIndex_unpredictable(i32 %n, ptr nocapture readonly %a) #0 {
; CHECK-NEXT: jl .LBB3_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: movl %edi, %ecx
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: movl $1, %edx
; CHECK-NEXT: .LBB3_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
Expand All @@ -387,7 +386,6 @@ define i32 @MaxIndex_unpredictable(i32 %n, ptr nocapture readonly %a) #0 {
; CHECK-FORCEALL-NEXT: jl .LBB3_3
; CHECK-FORCEALL-NEXT: # %bb.1: # %for.body.preheader
; CHECK-FORCEALL-NEXT: movl %edi, %ecx
; CHECK-FORCEALL-NEXT: xorl %eax, %eax
; CHECK-FORCEALL-NEXT: movl $1, %edx
; CHECK-FORCEALL-NEXT: .LBB3_2: # %for.body
; CHECK-FORCEALL-NEXT: # =>This Inner Loop Header: Depth=1
Expand Down
Loading