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[AArch64][llvm] Codegen for 16/32/64-bit floating-point atomicrmw fminimum/faximum #137703

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Merged
merged 1 commit into from
Apr 30, 2025
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[AArch64][llvm] Codegen for 16/32/64-bit floating-point atomicrmw fminimum/faximum #137703

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14 changes: 13 additions & 1 deletion llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1001,6 +1001,16 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::ATOMIC_LOAD_FMIN, MVT::f32, LibCall);
setOperationAction(ISD::ATOMIC_LOAD_FMIN, MVT::f64, LibCall);
setOperationAction(ISD::ATOMIC_LOAD_FMIN, MVT::bf16, LibCall);

setOperationAction(ISD::ATOMIC_LOAD_FMAXIMUM, MVT::f16, LibCall);
setOperationAction(ISD::ATOMIC_LOAD_FMAXIMUM, MVT::f32, LibCall);
setOperationAction(ISD::ATOMIC_LOAD_FMAXIMUM, MVT::f64, LibCall);
setOperationAction(ISD::ATOMIC_LOAD_FMAXIMUM, MVT::bf16, LibCall);

setOperationAction(ISD::ATOMIC_LOAD_FMINIMUM, MVT::f16, LibCall);
setOperationAction(ISD::ATOMIC_LOAD_FMINIMUM, MVT::f32, LibCall);
setOperationAction(ISD::ATOMIC_LOAD_FMINIMUM, MVT::f64, LibCall);
setOperationAction(ISD::ATOMIC_LOAD_FMINIMUM, MVT::bf16, LibCall);
}

if (Subtarget->hasLSE128()) {
Expand Down Expand Up @@ -27991,7 +28001,9 @@ AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
// If LSFE available, use atomic FP instructions in preference to expansion
if (Subtarget->hasLSFE() && (AI->getOperation() == AtomicRMWInst::FAdd ||
AI->getOperation() == AtomicRMWInst::FMax ||
AI->getOperation() == AtomicRMWInst::FMin))
AI->getOperation() == AtomicRMWInst::FMin ||
AI->getOperation() == AtomicRMWInst::FMaximum ||
AI->getOperation() == AtomicRMWInst::FMinimum))
return AtomicExpansionKind::None;

// Nand is not supported in LSE.
Expand Down
7 changes: 7 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrAtomics.td
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Expand Up @@ -551,14 +551,21 @@ defm atomic_load_fadd : binary_atomic_op_fp<atomic_load_fadd>;
defm atomic_load_fmin : binary_atomic_op_fp<atomic_load_fmin>;
defm atomic_load_fmax : binary_atomic_op_fp<atomic_load_fmax>;

defm atomic_load_fminimum : binary_atomic_op_fp<atomic_load_fminimum>;
defm atomic_load_fmaximum : binary_atomic_op_fp<atomic_load_fmaximum>;

let Predicates = [HasLSFE] in {
defm : LDFPOPregister_patterns<"LDFADD", "atomic_load_fadd">;
defm : LDFPOPregister_patterns<"LDFMAXNM", "atomic_load_fmax">;
defm : LDFPOPregister_patterns<"LDFMINNM", "atomic_load_fmin">;
defm : LDFPOPregister_patterns<"LDFMAX", "atomic_load_fmaximum">;
defm : LDFPOPregister_patterns<"LDFMIN", "atomic_load_fminimum">;

defm : LDBFPOPregister_patterns<"LDBFADD", "atomic_load_fadd">;
defm : LDBFPOPregister_patterns<"LDBFMAXNM", "atomic_load_fmax">;
defm : LDBFPOPregister_patterns<"LDBFMINNM", "atomic_load_fmin">;
defm : LDBFPOPregister_patterns<"LDBFMAX", "atomic_load_fmaximum">;
defm : LDBFPOPregister_patterns<"LDBFMIN", "atomic_load_fminimum">;
}

// v8.9a/v9.4a FEAT_LRCPC patterns
Expand Down
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