[Xtensa] Implement Xtensa Region Protection Option and several other small Options.

llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp

@@ -105,28 +105,37 @@ static const MCPhysReg MR23DecoderTable[] = {Xtensa::M2, Xtensa::M3};
 static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const void *Decoder) {
-  if (RegNo != 2 && RegNo != 3)
+  if (RegNo != 0 && RegNo != 1)
     return MCDisassembler::Fail;
 
-  MCPhysReg Reg = MR23DecoderTable[RegNo - 2];
+  MCPhysReg Reg = MR23DecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
-const MCPhysReg SRDecoderTable[] = {
-    Xtensa::SAR, 3,  Xtensa::ACCLO,      16, Xtensa::ACCHI,       17,
-    Xtensa::M0,  32, Xtensa::M1,         33, Xtensa::M2,          34,
-    Xtensa::M3,  35, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73};
+struct DecodeRegister {
+  MCPhysReg Reg;
+  uint32_t RegNo;
+};
+
+const DecodeRegister SRDecoderTable[] = {
+    {Xtensa::LBEG, 0},    {Xtensa::LEND, 1},        {Xtensa::LCOUNT, 2},
+    {Xtensa::SAR, 3},     {Xtensa::BREG, 4},        {Xtensa::SAR, 3},
+    {Xtensa::LITBASE, 5}, {Xtensa::ACCLO, 16},      {Xtensa::ACCHI, 17},
+    {Xtensa::M0, 32},     {Xtensa::M1, 33},         {Xtensa::M2, 34},
+    {Xtensa::M3, 35},     {Xtensa::WINDOWBASE, 72}, {Xtensa::WINDOWSTART, 73},
+    {Xtensa::MEMCTL, 97}, {Xtensa::VECBASE, 231},   {Xtensa::MISC0, 244},
+    {Xtensa::MISC1, 245}, {Xtensa::MISC2, 246},     {Xtensa::MISC3, 247}};
 
 static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
                                           uint64_t Address,
                                           const MCDisassembler *Decoder) {
   if (RegNo > 255)
     return MCDisassembler::Fail;
 
-  for (unsigned i = 0; i < std::size(SRDecoderTable); i += 2) {
-    if (SRDecoderTable[i + 1] == RegNo) {
-      MCPhysReg Reg = SRDecoderTable[i];
+  for (unsigned i = 0; i < std::size(SRDecoderTable); i++) {
+    if (SRDecoderTable[i].RegNo == RegNo) {
+      MCPhysReg Reg = SRDecoderTable[i].Reg;
 
       if (!Xtensa::checkRegister(Reg,
                                  Decoder->getSubtargetInfo().getFeatureBits()))

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp

@@ -83,6 +83,24 @@ bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits) {
   case Xtensa::LEND:
   case Xtensa::LCOUNT:
     return FeatureBits[Xtensa::FeatureLoop];
+  case Xtensa::LITBASE:
+    return FeatureBits[Xtensa::FeatureExtendedL32R];
+  case Xtensa::MEMCTL:
+    return FeatureBits[Xtensa::FeatureDataCache];
+  case Xtensa::ACCLO:
+  case Xtensa::ACCHI:
+  case Xtensa::M0:
+  case Xtensa::M1:
+  case Xtensa::M2:
+  case Xtensa::M3:
+    return FeatureBits[Xtensa::FeatureMAC16];
+  case Xtensa::MISC0:
+  case Xtensa::MISC1:
+  case Xtensa::MISC2:
+  case Xtensa::MISC3:
+    return FeatureBits[Xtensa::FeatureMiscSR];
+  case Xtensa::VECBASE:
+    return FeatureBits[Xtensa::FeatureRelocatableVector];
   case Xtensa::WINDOWBASE:
   case Xtensa::WINDOWSTART:
     return FeatureBits[Xtensa::FeatureWindowed];

llvm/lib/Target/Xtensa/XtensaFeatures.td

@@ -67,3 +67,28 @@ def FeatureDiv32 : SubtargetFeature<"div32", "HasDiv32", "true",
                                     "Enable Xtensa Div32 option">;
 def HasDiv32 : Predicate<"Subtarget->hasDiv32()">,
                AssemblerPredicate<(all_of FeatureDiv32)>;
+
+def FeatureRegionProtection : SubtargetFeature<"regprotect", "HasRegionProtection", "true",
+                                               "Enable Xtensa Region Protection option">;
+def HasRegionProtection : Predicate<"Subtarget->hasRegionProtection()">,
+                          AssemblerPredicate<(all_of FeatureRegionProtection)>;
+
+def FeatureRelocatableVector : SubtargetFeature<"rvector", "HasRelocatableVector", "true",
+                                                "Enable Xtensa Relocatable Vector option">;
+def HasRelocatableVector : Predicate<"Subtarget->hasRelocatableVector()">,
+                           AssemblerPredicate<(all_of FeatureRelocatableVector)>;
+
+def FeatureMiscSR : SubtargetFeature<"miscsr", "HasMiscSR", "true",
+                                     "Enable Xtensa Miscellaneous SR option">;
+def HasMiscSR : Predicate<"Subtarget->hasMiscSR()">,
+                AssemblerPredicate<(all_of FeatureMiscSR)>;
+
+def FeatureExtendedL32R : SubtargetFeature<"extendedl32r", "HasExtendedL32R", "true",
+                                           "Enable Xtensa Extended L32R option">;
+def HasExtendedL32R : Predicate<"Subtarget->hasExtendedL32R()">,
+                      AssemblerPredicate<(all_of FeatureExtendedL32R)>;
+
+def FeatureDataCache : SubtargetFeature<"dcache", "HasDataCache", "true",
+                                        "Enable Xtensa Data Cache option">;
+def HasDataCache : Predicate<"Subtarget->hasDataCache()">,
+                   AssemblerPredicate<(all_of FeatureDataCache)>;

llvm/lib/Target/Xtensa/XtensaInstrInfo.td

@@ -986,6 +986,64 @@ let Predicates = [HasDiv32] in {
   def REMU : ArithLogic_RRR<0x0E, 0x02, "remu", urem>;
 }
 
+//===----------------------------------------------------------------------===//
+// Region Protection feature instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasRegionProtection] in {
+  def IDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs), (ins AR:$s),
+                     "idtlb\t$s", []> {
+    let r = 0xC;
+	  let t = 0x0;
+  }
+
+  def IITLB : RRR_Inst<0x00, 0x00, 0x05, (outs), (ins AR:$s),
+                     "iitlb\t$s", []> {
+    let r = 0x4;
+	  let t = 0x0;
+  }
+
+  def PDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+                     "pdtlb\t$t, $s", []> {
+    let r = 0xD;
+  }
+
+  def PITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+                     "pitlb\t$t, $s", []> {
+    let r = 0x5;
+  }
+
+  def RDTLB0 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+                     "rdtlb0\t$t, $s", []> {
+    let r = 0xB;
+  }
+
+  def RDTLB1 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+                     "rdtlb1\t$t, $s", []> {
+    let r = 0xF;
+  }
+
+  def RITLB0 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+                     "ritlb0\t$t, $s", []> {
+    let r = 0x3;
+  }
+
+  def RITLB1 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+                     "ritlb1\t$t, $s", []> {
+    let r = 0x7;
+  }
+
+  def WDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+                     "wdtlb\t$t, $s", []> {
+    let r = 0xE;
+  }
+
+  def WITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+                      "witlb\t$t, $s", []> {
+    let r = 0x6;
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // DSP Instructions
 //===----------------------------------------------------------------------===//

llvm/lib/Target/Xtensa/XtensaRegisterInfo.td

@@ -84,10 +84,25 @@ def SAR : SRReg<3, "sar", ["SAR","3"]>;
 // Boolean Register
 def BREG : SRReg<4, "br", ["BR","4"]>;
 
+// Literal base
+def LITBASE : SRReg<5, "litbase", ["LITBASE", "5"]>;
+
 // Windowed Register Option registers
 def WINDOWBASE : SRReg<72, "windowbase", ["WINDOWBASE", "72"]>;
 def WINDOWSTART : SRReg<73, "windowstart", ["WINDOWSTART", "73"]>;
 
+// Memory Control Register
+def MEMCTL : SRReg<97, "memctl", ["MEMCTL", "97"]>;
+
+// Vector base register
+def VECBASE : SRReg<231, "vecbase", ["VECBASE", "231"]>;
+
+// Xtensa Miscellaneous SR
+def MISC0 : SRReg<244, "misc0", ["MISC0", "244"]>;
+def MISC1 : SRReg<245, "misc1", ["MISC1", "245"]>;
+def MISC2 : SRReg<246, "misc2", ["MISC2", "246"]>;
+def MISC3 : SRReg<247, "misc3", ["MISC3", "247"]>;
+
 // MAC16 Option registers
 def ACCLO : SRReg<16, "acclo", ["ACCLO", "16"]>;
 def ACCHI : SRReg<17, "acchi", ["ACCHI", "17"]>;
@@ -101,7 +116,8 @@ def MR23 :  RegisterClass<"Xtensa", [i32], 32, (add M2, M3)>;
 def MR   :  RegisterClass<"Xtensa", [i32], 32, (add MR01, MR23)>;
 
 def SR :  RegisterClass<"Xtensa", [i32], 32, (add
-  LBEG, LEND, LCOUNT, SAR, BREG, MR, WINDOWBASE, WINDOWSTART)>;
+  LBEG, LEND, LCOUNT, SAR, BREG, LITBASE, ACCLO, ACCHI, MR, WINDOWBASE, WINDOWSTART,
+  MEMCTL, VECBASE, MISC0, MISC1, MISC2, MISC3)>;
 
 //===----------------------------------------------------------------------===//
 // Boolean registers

llvm/lib/Target/Xtensa/XtensaSubtarget.h

@@ -77,6 +77,11 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
   bool hasMul32() const { return HasMul32; }
   bool hasMul32High() const { return HasMul32High; }
   bool hasDiv32() const { return HasDiv32; }
+  bool hasRegionProtection() const { return HasRegionProtection; }
+  bool hasRelocatableVector() const { return HasRelocatableVector; }
+  bool hasMiscSR() const { return HasMiscSR; }
+  bool hasExtendedL32R() const { return HasExtendedL32R; }
+  bool hasDataCache() const { return HasDataCache; }
   bool isWindowedABI() const { return hasWindowed(); }
 
   // Automatically generated by tblgen.

llvm/test/MC/Disassembler/Xtensa/clamps.txt

@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+clamps -disassemble %s | FileCheck -check-prefixes=CHECK-CLAMPS %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## clamps option enabled. Also verify that dissasembling without
+## clamps option generates warnings.
+
+[0x00,0x34,0x33]
+# CHECK-CLAMPS: clamps a3, a4, 7
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding

llvm/test/MC/Disassembler/Xtensa/code_density.txt

@@ -1,11 +1,9 @@
 # RUN: llvm-mc -triple=xtensa -mattr=+density -disassemble %s | FileCheck -check-prefixes=CHECK-DENSITY %s
 # RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
 
-#------------------------------------------------------------------------------
-# Verify that binary code is correctly disassembled with
-# code density option enabled. Also verify that dissasembling without
-# density option generates warnings.
-#------------------------------------------------------------------------------
+## Verify that binary code is correctly disassembled with
+## code density option enabled. Also verify that dissasembling without
+## density option generates warnings.
 
 [0x4a, 0x23]
 # CHECK-DENSITY: add.n  a2, a3, a4

llvm/test/MC/Disassembler/Xtensa/dcache.txt

@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+dcache -disassemble %s | FileCheck -check-prefixes=CHECK-DCACHE %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## dcache option enabled. Also verify that dissasembling without
+## dcache option generates warnings.
+
+[0x30,0x61,0x61]
+# CHECK-DCACHE: xsr a3, memctl
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding

llvm/test/MC/Disassembler/Xtensa/div.txt

@@ -0,0 +1,22 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+div32 -disassemble %s | FileCheck -check-prefixes=CHECK-DIV32 %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## div32 option enabled. Also verify that dissasembling without
+## div32 option generates warnings.
+
+[0x50,0x34,0xd2]
+# CHECK-DIV32: quos a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x50,0x34,0xc2]
+# CHECK-DIV32: quou a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x50,0x34,0xf2]
+# CHECK-DIV32: rems a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x50,0x34,0xe2]
+# CHECK-DIV32: remu a3, a4, a5
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding

llvm/test/MC/Disassembler/Xtensa/extendedl32r.txt

@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+extendedl32r -disassemble %s | FileCheck -check-prefixes=CHECK-EXTENDEDL32R %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## extendedl32r option enabled. Also verify that dissasembling without
+## extendedl32r option generates warnings.
+
+[0x30,0x05,0x61]
+# CHECK-EXTENDEDL32R: xsr a3, litbase
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding

llvm/test/MC/Disassembler/Xtensa/loop.txt

@@ -0,0 +1,30 @@
+# RUN: llvm-mc -triple=xtensa -mattr=+loop -disassemble %s | FileCheck -check-prefixes=CHECK-LOOP %s
+# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
+
+## Verify that binary code is correctly disassembled with
+## loop option enabled. Also verify that dissasembling without
+## loop option generates warnings.
+
+[0x76,0x83,0x40]
+# CHECK-LOOP: loop a3, . +68
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x76,0x93,0x40]
+# CHECK-LOOP: loopnez a3, . +68
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x76,0xa3,0x40]
+# CHECK-LOOP: loopgtz a3, . +68
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0x00,0x61]
+# CHECK-LOOP: xsr a3, lbeg
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0x01,0x61]
+# CHECK-LOOP: xsr a3, lend
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x30,0x02,0x61]
+# CHECK-LOOP: xsr a3, lcount
+# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding