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[SelectionDAG][RISCV] Teach computeKnownBits to use range metadata for atomic_load. #137119

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Merged
merged 3 commits into from
Apr 24, 2025
Merged

[SelectionDAG][RISCV] Teach computeKnownBits to use range metadata for atomic_load. #137119

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Pre-commit tests
topperc Apr 24, 2025
5abee2b
[SelectionDAG][RISCV] Teach computeKnownBits to use range metadata fo…
topperc Apr 24, 2025
3ad8b9a
fixup! Use switch
topperc Apr 24, 2025
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49 changes: 39 additions & 10 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4382,6 +4382,43 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
Known.Zero |= APInt::getBitsSetFrom(BitWidth, VT.getScalarSizeInBits());
break;
}
case ISD::ATOMIC_LOAD: {
// If we are looking at the loaded value.
if (Op.getResNo() == 0) {
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(minor) Possibly could be an assertion, chain result is not a part of data flow

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I was keeping consistency with ISD::LOAD. Maybe we should change all of them at once?

auto *AT = cast<AtomicSDNode>(Op);
unsigned ScalarMemorySize = AT->getMemoryVT().getScalarSizeInBits();
KnownBits KnownScalarMemory(ScalarMemorySize);
if (const MDNode *MD = AT->getRanges())
computeKnownBitsFromRangeMetadata(*MD, KnownScalarMemory);

switch (AT->getExtensionType()) {
case ISD::ZEXTLOAD:
Known = KnownScalarMemory.zext(BitWidth);
break;
case ISD::SEXTLOAD:
Known = KnownScalarMemory.sext(BitWidth);
break;
case ISD::EXTLOAD:
switch (TLI->getExtendForAtomicOps()) {
case ISD::ZERO_EXTEND:
Known = KnownScalarMemory.zext(BitWidth);
break;
case ISD::SIGN_EXTEND:
Known = KnownScalarMemory.sext(BitWidth);
break;
default:
Known = KnownScalarMemory.anyext(BitWidth);
break;
}
break;
case ISD::NON_EXTLOAD:
Known = KnownScalarMemory;
break;
}
assert(Known.getBitWidth() == BitWidth);
}
break;
}
case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
if (Op.getResNo() == 1) {
// The boolean result conforms to getBooleanContents.
Expand All @@ -4407,21 +4444,13 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
case ISD::ATOMIC_LOAD_MIN:
case ISD::ATOMIC_LOAD_MAX:
case ISD::ATOMIC_LOAD_UMIN:
case ISD::ATOMIC_LOAD_UMAX:
case ISD::ATOMIC_LOAD: {
case ISD::ATOMIC_LOAD_UMAX: {
// If we are looking at the loaded value.
if (Op.getResNo() == 0) {
auto *AT = cast<AtomicSDNode>(Op);
unsigned MemBits = AT->getMemoryVT().getScalarSizeInBits();

// For atomic_load, prefer to use the extension type.
if (Op->getOpcode() == ISD::ATOMIC_LOAD) {
if (AT->getExtensionType() == ISD::ZEXTLOAD)
Known.Zero.setBitsFrom(MemBits);
else if (AT->getExtensionType() != ISD::SEXTLOAD &&
TLI->getExtendForAtomicOps() == ISD::ZERO_EXTEND)
Known.Zero.setBitsFrom(MemBits);
} else if (TLI->getExtendForAtomicOps() == ISD::ZERO_EXTEND)
if (TLI->getExtendForAtomicOps() == ISD::ZERO_EXTEND)
Known.Zero.setBitsFrom(MemBits);
}
break;
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3 changes: 2 additions & 1 deletion llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5150,9 +5150,10 @@ void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {

auto Flags = TLI.getLoadMemOperandFlags(I, DAG.getDataLayout(), AC, LibInfo);

const MDNode *Ranges = getRangeMetadata(I);
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
MachinePointerInfo(I.getPointerOperand()), Flags, MemVT.getStoreSize(),
I.getAlign(), AAMDNodes(), nullptr, SSID, Order);
I.getAlign(), AAMDNodes(), Ranges, SSID, Order);

InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);

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