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Merged
merged 4 commits into from
Apr 22, 2025
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@kuhar kuhar commented Apr 22, 2025

We know that the index of unit dims is always 0.

We know that the index of unit dims is always 0.
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llvmbot commented Apr 22, 2025

@llvm/pr-subscribers-mlir-linalg

@llvm/pr-subscribers-mlir

Author: Jakub Kuderski (kuhar)

Changes

We know that the index of unit dims is always 0.


Full diff: https://github.com/llvm/llvm-project/pull/136640.diff

3 Files Affected:

  • (modified) mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td (+1)
  • (modified) mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp (+29)
  • (modified) mlir/test/Dialect/Linalg/canonicalize.mlir (+80)
diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td b/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
index f8df828f74851..1b48bf5fcb237 100644
--- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
+++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
@@ -88,6 +88,7 @@ def Linalg_IndexOp : Linalg_Op<"index", [Pure]>,
 
   let assemblyFormat = [{ $dim attr-dict `:` type($result) }];
   let hasVerifier = 1;
+  let hasFolder = 1;
 }
 
 def Linalg_SoftmaxOp : Linalg_Op<"softmax",
diff --git a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
index 6c680498af2ad..a3787f101afa3 100644
--- a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
+++ b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
@@ -2283,6 +2283,35 @@ LogicalResult IndexOp::verify() {
   return success();
 }
 
+OpFoldResult IndexOp::fold(FoldAdaptor adaptor) {
+  auto linalgOp = cast<LinalgOp>((*this)->getParentOp());
+  int64_t flatDimPos =
+      cast<AffineDimExpr>(linalgOp.getShapesToLoopsMap().getResult(getDim()))
+          .getPosition();
+
+  // Find the flat dimension position among the operands.
+  int64_t flatPosOffset = 0;
+  for (Value operand : linalgOp->getOperands()) {
+    assert(flatDimPos >= flatPosOffset && "invalid position");
+    auto shapedType = dyn_cast<ShapedType>(operand.getType());
+    if (!shapedType)
+      break;
+
+    int64_t rank = shapedType.getRank();
+    if (flatDimPos < flatPosOffset + rank) {
+      // Found the dimension within this shape. Now we can either fold if the
+      // dim size is 1, or bail out otherwise.
+      int64_t pos = flatDimPos - flatPosOffset;
+      if (shapedType.getDimSize(pos) != 1)
+        break;
+
+      return IntegerAttr::get(IndexType::get(getContext()), 0);
+    }
+    flatPosOffset += rank;
+  }
+  return OpFoldResult{};
+}
+
 /////// Operations corresponding to library calls defined with Tablegen ////////
 
 #include "mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yamlgen.cpp.inc"
diff --git a/mlir/test/Dialect/Linalg/canonicalize.mlir b/mlir/test/Dialect/Linalg/canonicalize.mlir
index 86cb8f58abe02..3daf221f4402d 100644
--- a/mlir/test/Dialect/Linalg/canonicalize.mlir
+++ b/mlir/test/Dialect/Linalg/canonicalize.mlir
@@ -305,6 +305,86 @@ func.func @self_copy(%arg0 : memref<2x3x?x4xf32>) {
 }
 
 // -----
+
+// CHECK: func @fold_linalg_index_tensor_static
+func.func @fold_linalg_index_tensor_static(%0: tensor<4x16xi32>, %1: tensor<1x16xi32>,
+                                           %2: tensor<4x1xi32>) -> tensor<4x1xi32> {
+// CHECK-NEXT: linalg.generic
+// CHECK:        %[[IDX_0:.+]] = linalg.index 0 : index
+// CHECK-NOT:    linalg.index 1
+// CHECK:        %[[IDX_2:.+]] = linalg.index 2 : index
+// CHECK:        %[[ADD:.+]] = arith.addi %[[IDX_0]], %[[IDX_2]]
+// CHECK:        %[[CAST:.+]] = arith.index_cast %[[ADD]]
+// CHECK:        linalg.yield %[[CAST]]
+  %res = linalg.generic {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>,
+                                          affine_map<(d0, d1, d2) -> (d1, d2)>,
+                                          affine_map<(d0, d1, d2) -> (d0, d1)>],
+                         iterator_types = ["parallel", "parallel", "reduction"]}
+    ins(%0, %1 : tensor<4x16xi32>, tensor<1x16xi32>)
+    outs(%2 : tensor<4x1xi32>) {
+      ^bb0(%lhs: i32, %rhs: i32, %out: i32):
+        %idx0 = linalg.index 0 : index
+        %idx1 = linalg.index 1 : index
+        %idx2 = linalg.index 2 : index
+        %add0 = arith.addi %idx0, %idx1 : index
+        %add1 = arith.addi %add0, %idx2 : index
+        %int = arith.index_cast %add1 : index to i32
+        linalg.yield %int : i32
+    } -> tensor<4x1xi32>
+  return %res : tensor<4x1xi32>
+}
+
+// -----
+
+// CHECK: func @fold_linalg_index_tensor_dynamic
+func.func @fold_linalg_index_tensor_dynamic(%0: tensor<?x1xi32>,
+                                            %1: tensor<?x1xi32>) -> tensor<?x1xi32> {
+// CHECK-NEXT: linalg.generic
+// CHECK:        %[[IDX_0:.+]] = linalg.index 0 : index
+// CHECK-NOT:    linalg.index 1
+// CHECK:        %[[CAST:.+]] = arith.index_cast %[[IDX_0]]
+// CHECK:        linalg.yield %[[CAST]]
+  %res = linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>,
+                                          affine_map<(d0, d1) -> (d1, d1)>],
+                         iterator_types = ["parallel", "parallel"]}
+    ins(%0 : tensor<?x1xi32>)
+    outs(%1 : tensor<?x1xi32>) {
+      ^bb0(%lhs: i32, %out: i32):
+        %idx0 = linalg.index 0 : index
+        %idx1 = linalg.index 1 : index
+        %add = arith.addi %idx0, %idx1 : index
+        %int = arith.index_cast %add : index to i32
+        linalg.yield %int : i32
+    } -> tensor<?x1xi32>
+  return %res : tensor<?x1xi32>
+}
+
+// -----
+
+// CHECK: func @fold_linalg_index_memref
+func.func @fold_linalg_index_memref(%0: memref<1x?xi32>, %1: memref<1x?xi32>) {
+// CHECK-NEXT: linalg.generic
+// CHECK-NOT:    linalg.index 0
+// CHECK:        %[[IDX_1:.+]] = linalg.index 1 : index
+// CHECK:        %[[CAST:.+]] = arith.index_cast %[[IDX_1]]
+// CHECK:        linalg.yield %[[CAST]]
+  linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>,
+                                   affine_map<(d0, d1) -> (d1, d1)>],
+                  iterator_types = ["parallel", "parallel"]}
+    ins(%0 : memref<1x?xi32>)
+    outs(%1 : memref<1x?xi32>) {
+      ^bb0(%lhs: i32, %out: i32):
+        %idx0 = linalg.index 0 : index
+        %idx1 = linalg.index 1 : index
+        %add = arith.addi %idx0, %idx1 : index
+        %int = arith.index_cast %add : index to i32
+        linalg.yield %int : i32
+    }
+  return
+}
+
+// -----
+
 // CHECK-LABEL: func @fold_fill_reshape()
 func.func @fold_fill_reshape() -> tensor<6x4xf32> {
   %zero = arith.constant 0.0 : f32

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Makes sense, thanks!

I've left some nits/side-comments. Feel free to ignore.

@kuhar kuhar merged commit f010725 into llvm:main Apr 22, 2025
6 of 9 checks passed
raikonenfnu added a commit to raikonenfnu/iree that referenced this pull request Apr 24, 2025
LIT change because of llvm/llvm-project#136640 which folds linalg.index
who are unit dims.

This patch carries revert of

llvm/llvm-project#137122. StableHLO and Torch-mlir needs to update their
usage of GreedyRewriteConfig to use fluent API. i.e
enableRegionSimplification = VS setRegionSimplificationLevel

llvm/llvm-project#135970. StableHLO has issue with VHLO_IntegerAttr and APInt not being updated. StableHLO needs to be updated with that PR's change for us to be able to integrate.

llvm/llvm-project#121389. Torch-MLIR needs to be
updated with that PR's change for us to be able to integrate.

Signed-off-by: Stanley Winata <stanley.winata@amd.com>
raikonenfnu added a commit to raikonenfnu/iree that referenced this pull request Apr 24, 2025
LIT change because of llvm/llvm-project#136640 which folds linalg.index
who are unit dims.

This patch carries revert of:

llvm/llvm-project#137122. StableHLO and Torch-mlir needs to update their
usage of GreedyRewriteConfig to use fluent API. i.e
enableRegionSimplification = VS setRegionSimplificationLevel

llvm/llvm-project#135970. StableHLO has issue with VHLO_IntegerAttr and APInt not being updated. StableHLO needs to be updated with that PR's change for us to be able to integrate.

llvm/llvm-project#121389. Torch-MLIR needs to be
updated with that PR's change for us to be able to integrate.

Signed-off-by: Stanley Winata <stanley.winata@amd.com>
raikonenfnu added a commit to iree-org/llvm-project that referenced this pull request Apr 25, 2025
raikonenfnu added a commit to raikonenfnu/iree that referenced this pull request Apr 25, 2025
This patch carries revert of

llvm/llvm-project#136640 because linalg.index folder is segfaulting on inceptionv2 model

llvm/llvm-project#133231. This PR breaks fp_to_subbytes and emulation_subbyte_types on llvm-cpu tests. iree-test-deps.

llvm/llvm-project#137122. StableHLO and Torch-mlir needs to update their usage of GreedyRewriteConfig to use fluent API. i.e enableRegionSimplification = VS setRegionSimplificationLevel

llvm/llvm-project#135970. StableHLO has issue with VHLO_IntegerAttr and APInt not being updated. StableHLO needs to be updated with that PR's change for us to be able to integrate.

llvm/llvm-project#121389. Torch-MLIR needs to be
updated with that PR's change for us to be able to integrate.

Signed-off-by: Stanley Winata <stanley.winata@amd.com>
raikonenfnu added a commit to iree-org/llvm-project that referenced this pull request Apr 25, 2025
raikonenfnu added a commit to raikonenfnu/iree that referenced this pull request Apr 25, 2025
This patch carries revert of:

llvm/llvm-project#136640 because linalg.index folder is segfaulting on inceptionv2 model

llvm/llvm-project#133231. This PR breaks fp_to_subbytes and emulation_subbyte_types on llvm-cpu tests. iree-test-deps.

llvm/llvm-project#137122. StableHLO and Torch-mlir needs to update their usage of GreedyRewriteConfig to use fluent API. i.e enableRegionSimplification = VS setRegionSimplificationLevel

llvm/llvm-project#135970. StableHLO has issue with VHLO_IntegerAttr and APInt not being updated. StableHLO needs to be updated with that PR's change for us to be able to integrate.

llvm/llvm-project#121389. Torch-MLIR needs to be
updated with that PR's change for us to be able to integrate.

Signed-off-by: Stanley Winata <stanley.winata@amd.com>
raikonenfnu added a commit to iree-org/iree that referenced this pull request Apr 25, 2025
This patch carries revert of

llvm/llvm-project#136640 because linalg.index folder is segfaulting on
inceptionv2 model

llvm/llvm-project#133231. This PR breaks fp_to_subbytes and
emulation_subbyte_types on llvm-cpu tests. iree-test-deps.

llvm/llvm-project#137122. StableHLO and Torch-mlir needs to update their
usage of GreedyRewriteConfig to use fluent API. i.e
enableRegionSimplification = VS setRegionSimplificationLevel

llvm/llvm-project#135970. StableHLO has issue with VHLO_IntegerAttr and
APInt not being updated. StableHLO needs to be updated with that PR's
change for us to be able to integrate.

llvm/llvm-project#121389. Torch-MLIR needs to be
updated with that PR's change for us to be able to integrate.

Signed-off-by: Stanley Winata <stanley.winata@amd.com>
raikonenfnu added a commit to raikonenfnu/iree that referenced this pull request Apr 26, 2025
Updated LIT test from landing llvm/llvm-project#136640
which folds linalg.index when size is unit dim (1).

This patch carries revert of

llvm/llvm-project#133231. This PR breaks fp_to_subbytes and
emulation_subbyte_types on llvm-cpu tests. iree-test-deps.

llvm/llvm-project#137122. StableHLO and Torch-mlir needs to update their
usage of GreedyRewriteConfig to use fluent API. i.e
enableRegionSimplification = VS setRegionSimplificationLevel

llvm/llvm-project#135970. StableHLO has issue with VHLO_IntegerAttr and
APInt not being updated. StableHLO needs to be updated with that PR's
change for us to be able to integrate.

llvm/llvm-project#121389. Torch-MLIR needs to be
updated with that PR's change for us to be able to integrate.

Signed-off-by: Stanley Winata <stanley.winata@amd.com>
raikonenfnu added a commit to raikonenfnu/iree that referenced this pull request Apr 26, 2025
Updated LIT test from landing llvm/llvm-project#136640
which folds linalg.index when size is unit dim (1).

This patch carries revert of

llvm/llvm-project#133231. This PR breaks fp_to_subbytes and
emulation_subbyte_types on llvm-cpu tests. iree-test-deps.
tracking issue in iree-org#20645.

llvm/llvm-project#137122. StableHLO and Torch-mlir needs to update their
usage of GreedyRewriteConfig to use fluent API. i.e
enableRegionSimplification = VS setRegionSimplificationLevel

llvm/llvm-project#135970. StableHLO has issue with VHLO_IntegerAttr and
APInt not being updated. StableHLO needs to be updated with that PR's
change for us to be able to integrate.

llvm/llvm-project#121389. Torch-MLIR needs to be
updated with that PR's change for us to be able to integrate.

Signed-off-by: Stanley Winata <stanley.winata@amd.com>
raikonenfnu added a commit to iree-org/iree that referenced this pull request Apr 26, 2025
Updated LIT test from landing llvm/llvm-project#136640 which folds
linalg.index when size is unit dim (1).

Added chipSet argument into populateGpuToROCDLConversionPatterns based
on changes in llvm/llvm-project#137360

This patch carries revert of

llvm/llvm-project#133231. This PR breaks fp_to_subbytes and
emulation_subbyte_types on llvm-cpu tests. iree-test-deps. tracker issue
in #20645.

llvm/llvm-project#137122. StableHLO and Torch-mlir needs to update their
usage of GreedyRewriteConfig to use fluent API. i.e
enableRegionSimplification = VS setRegionSimplificationLevel

llvm/llvm-project#135970. StableHLO has issue with VHLO_IntegerAttr and
APInt not being updated. StableHLO needs to be updated with that PR's
change for us to be able to integrate.

llvm/llvm-project#121389. Torch-MLIR needs to be
updated with that PR's change for us to be able to integrate.

---------

Signed-off-by: Stanley Winata <stanley.winata@amd.com>
IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025
We know that the index of unit dims is always 0.
IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025
We know that the index of unit dims is always 0.
IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025
We know that the index of unit dims is always 0.
KyleHerndon pushed a commit to KyleHerndon/iree that referenced this pull request May 7, 2025
This patch carries revert of

llvm/llvm-project#136640 because linalg.index folder is segfaulting on
inceptionv2 model

llvm/llvm-project#133231. This PR breaks fp_to_subbytes and
emulation_subbyte_types on llvm-cpu tests. iree-test-deps.

llvm/llvm-project#137122. StableHLO and Torch-mlir needs to update their
usage of GreedyRewriteConfig to use fluent API. i.e
enableRegionSimplification = VS setRegionSimplificationLevel

llvm/llvm-project#135970. StableHLO has issue with VHLO_IntegerAttr and
APInt not being updated. StableHLO needs to be updated with that PR's
change for us to be able to integrate.

llvm/llvm-project#121389. Torch-MLIR needs to be
updated with that PR's change for us to be able to integrate.

Signed-off-by: Stanley Winata <stanley.winata@amd.com>
KyleHerndon pushed a commit to KyleHerndon/iree that referenced this pull request May 7, 2025
Updated LIT test from landing llvm/llvm-project#136640 which folds
linalg.index when size is unit dim (1).

Added chipSet argument into populateGpuToROCDLConversionPatterns based
on changes in llvm/llvm-project#137360

This patch carries revert of

llvm/llvm-project#133231. This PR breaks fp_to_subbytes and
emulation_subbyte_types on llvm-cpu tests. iree-test-deps. tracker issue
in iree-org#20645.

llvm/llvm-project#137122. StableHLO and Torch-mlir needs to update their
usage of GreedyRewriteConfig to use fluent API. i.e
enableRegionSimplification = VS setRegionSimplificationLevel

llvm/llvm-project#135970. StableHLO has issue with VHLO_IntegerAttr and
APInt not being updated. StableHLO needs to be updated with that PR's
change for us to be able to integrate.

llvm/llvm-project#121389. Torch-MLIR needs to be
updated with that PR's change for us to be able to integrate.

---------

Signed-off-by: Stanley Winata <stanley.winata@amd.com>
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7 participants