Skip to content

[RISCV] Add smcntrpmf extension #136556

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Apr 22, 2025
Merged

[RISCV] Add smcntrpmf extension #136556

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions clang/test/Driver/print-supported-extensions-riscv.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -123,6 +123,7 @@
// CHECK-NEXT: shvstvecd 1.0 'Shvstvecd' (vstvec supports Direct mode)
// CHECK-NEXT: smaia 1.0 'Smaia' (Advanced Interrupt Architecture Machine Level)
// CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level)
// CHECK-NEXT: smcntrpmf 1.0 'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering)
// CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level)
// CHECK-NEXT: smdbltrp 1.0 'Smdbltrp' (Double Trap Machine Level)
// CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection)
Expand Down
9 changes: 9 additions & 0 deletions clang/test/Preprocessor/riscv-target-features.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,7 @@
// CHECK-NOT: __riscv_shvstvecd {{.*$}}
// CHECK-NOT: __riscv_smaia {{.*$}}
// CHECK-NOT: __riscv_smcdeleg {{.*$}}
// CHECK-NOT: __riscv_smcntrpmf {{.*$}}
// CHECK-NOT: __riscv_smcsrind {{.*$}}
// CHECK-NOT: __riscv_smdbltrp {{.*$}}
// CHECK-NOT: __riscv_smepmp {{.*$}}
Expand Down Expand Up @@ -1445,6 +1446,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s
// CHECK-SSAIA-EXT: __riscv_ssaia 1000000{{$}}

// RUN: %clang --target=riscv32 \
// RUN: -march=rv32ismcntrpmf1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMCNTRPMF-EXT %s
// RUN: %clang --target=riscv64 \
// RUN: -march=rv64ismcntrpmf1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMCNTRPMF-EXT %s
// CHECK-SMCNTRPMF-EXT: __riscv_smcntrpmf 1000000{{$}}

// RUN: %clang --target=riscv32 \
// RUN: -march=rv32ismcsrind1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMCSRIND-EXT %s
Expand Down
1 change: 1 addition & 0 deletions llvm/docs/RISCVUsage.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -128,6 +128,7 @@ on support follow.
``Shvstvecd`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Smaia`` Supported
``Smcdeleg`` Supported
``Smcntrpmf`` Supported
``Smcsrind`` Supported
``Smdbltrp`` Supported
``Smepmp`` Supported
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -899,6 +899,9 @@ def FeatureStdExtSsaia
: RISCVExtension<1, 0,
"Advanced Interrupt Architecture Supervisor Level">;

def FeatureStdExtSmcntrpmf
: RISCVExtension<1, 0, "Cycle and Instret Privilege Mode Filtering">;

def FeatureStdExtSmcsrind
: RISCVExtension<1, 0, "Indirect CSR Access Machine Level">;
def FeatureStdExtSscsrind
Expand Down
10 changes: 10 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSystemOperands.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -482,6 +482,16 @@ def : SysReg<"sctrdepth", 0x15f>;
def : SysReg<"vsctrctl", 0x24e>;
def : SysReg<"mctrctl", 0x34e>;

//===-----------------------------------------------
// Cycle and Instret Privilege Mode Filtering (Smcntrpmf)
//===-----------------------------------------------
def : SysReg<"mcyclecfg", 0x321>;
def : SysReg<"minstretcfg", 0x322>;
let isRV32Only = 1 in {
def : SysReg<"mcyclecfgh", 0x721>;
def : SysReg<"minstretcfgh", 0x722>;
} // isRV32Only

//===-----------------------------------------------
// Vendor CSRs
//===-----------------------------------------------
Expand Down
4 changes: 4 additions & 0 deletions llvm/test/CodeGen/RISCV/attributes.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -147,6 +147,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SSDBLTRP %s
; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
; RUN: llc -mtriple=riscv32 -mattr=+smcntrpmf %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCNTRPMF %s
; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s
; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
Expand Down Expand Up @@ -301,6 +302,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SSDBLTRP %s
; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
; RUN: llc -mtriple=riscv64 -mattr=+smcntrpmf %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCNTRPMF %s
; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s
; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
Expand Down Expand Up @@ -485,6 +487,7 @@
; RV32SSDBLTRP: .attribute 5, "rv32i2p1_ssdbltrp1p0"
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
; RV32SMCNTRPMF: .attribute 5, "rv32i2p1_smcntrpmf1p0"
; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
Expand Down Expand Up @@ -636,6 +639,7 @@
; RV64SSDBLTRP: .attribute 5, "rv64i2p1_ssdbltrp1p0"
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
; RV64SMCNTRPMF: .attribute 5, "rv64i2p1_smcntrpmf1p0"
; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/RISCV/features-info.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -129,6 +129,7 @@
; CHECK-NEXT: sifive7 - SiFive 7-Series processors.
; CHECK-NEXT: smaia - 'Smaia' (Advanced Interrupt Architecture Machine Level).
; CHECK-NEXT: smcdeleg - 'Smcdeleg' (Counter Delegation Machine Level).
; CHECK-NEXT: smcntrpmf - 'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering).
; CHECK-NEXT: smcsrind - 'Smcsrind' (Indirect CSR Access Machine Level).
; CHECK-NEXT: smdbltrp - 'Smdbltrp' (Double Trap Machine Level).
; CHECK-NEXT: smepmp - 'Smepmp' (Enhanced Physical Memory Protection).
Expand Down
3 changes: 3 additions & 0 deletions llvm/test/MC/RISCV/attribute-arch.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -336,6 +336,9 @@
.attribute arch, "rv32i_smcdeleg1p0"
# CHECK: attribute 5, "rv32i2p1_smcdeleg1p0"

.attribute arch, "rv32i_smcntrpmf1p0"
# CHECK: attribute 5, "rv32i2p1_smcntrpmf1p0"

.attribute arch, "rv32i_smepmp1p0"
# CHECK: attribute 5, "rv32i2p1_smepmp1p0"

Expand Down
24 changes: 24 additions & 0 deletions llvm/test/MC/RISCV/machine-csr-names.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2733,3 +2733,27 @@ csrrs t2, 0x742, zero
csrrs t1, mnstatus, zero
# uimm12
csrrs t2, 0x744, zero

# mcyclecfg
# name
# CHECK-INST: csrrs t1, mcyclecfg, zero
# CHECK-ENC: encoding: [0x73,0x23,0x10,0x32]
# CHECK-INST-ALIAS: csrr t1, mcyclecfg
csrrs t1, mcyclecfg, zero
# uimm12
# CHECK-INST: csrrs t2, mcyclecfg, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x32]
# CHECK-INST-ALIAS: csrr t2, mcyclecfg
csrrs t2, 0x321, zero

# minstretcfg
# name
# CHECK-INST: csrrs t1, minstretcfg, zero
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x32]
# CHECK-INST-ALIAS: csrr t1, minstretcfg
csrrs t1, minstretcfg, zero
# uimm12
# CHECK-INST: csrrs t2, minstretcfg, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x32]
# CHECK-INST-ALIAS: csrr t2, minstretcfg
csrrs t2, 0x322, zero
24 changes: 24 additions & 0 deletions llvm/test/MC/RISCV/rv32-machine-csr-names.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1163,3 +1163,27 @@ csrrs t2, 0x319, zero
csrrs t1, miph, zero
# uimm12
csrrs t2, 0x354, zero

# mcyclecfgh
# name
# CHECK-INST: csrrs t1, mcyclecfgh, zero
# CHECK-ENC: encoding: [0x73,0x23,0x10,0x72]
# CHECK-INST-ALIAS: csrr t1, mcyclecfgh
csrrs t1, mcyclecfgh, zero
# uimm12
# CHECK-INST: csrrs t2, mcyclecfgh, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x72]
# CHECK-INST-ALIAS: csrr t2, mcyclecfgh
csrrs t2, 0x721, zero

# minstretcfgh
# name
# CHECK-INST: csrrs t1, minstretcfgh, zero
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x72]
# CHECK-INST-ALIAS: csrr t1, minstretcfgh
csrrs t1, minstretcfgh, zero
# uimm12
# CHECK-INST: csrrs t2, minstretcfgh, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x72]
# CHECK-INST-ALIAS: csrr t2, minstretcfgh
csrrs t2, 0x722, zero
1 change: 1 addition & 0 deletions llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1086,6 +1086,7 @@ R"(All available -march extensions for RISC-V
shvstvecd 1.0
smaia 1.0
smcdeleg 1.0
smcntrpmf 1.0
smcsrind 1.0
smdbltrp 1.0
smepmp 1.0
Expand Down
Loading