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[AMDGPU] add s_bitset[10]_b32 optimization for shl+[or,andn2] pattern #134155

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[AMDGPU] add s_bitset[10]_b32 optimization for shl+[or,andn2] pattern #134155

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71 changes: 69 additions & 2 deletions llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,7 @@
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineOperand.h"

#define DEBUG_TYPE "si-shrink-instructions"

Expand Down Expand Up @@ -44,6 +45,7 @@ class SIShrinkInstructions {
void shrinkMIMG(MachineInstr &MI) const;
void shrinkMadFma(MachineInstr &MI) const;
bool shrinkScalarLogicOp(MachineInstr &MI) const;
bool shrinkToBitset(MachineInstr &MI) const;
bool tryReplaceDeadSDST(MachineInstr &MI) const;
bool instAccessReg(iterator_range<MachineInstr::const_mop_iterator> &&R,
Register Reg, unsigned SubReg) const;
Expand Down Expand Up @@ -577,8 +579,7 @@ bool SIShrinkInstructions::shrinkScalarLogicOp(MachineInstr &MI) const {
const bool IsUndef = SrcReg->isUndef();
const bool IsKill = SrcReg->isKill();
MI.setDesc(TII->get(Opc));
if (Opc == AMDGPU::S_BITSET0_B32 ||
Opc == AMDGPU::S_BITSET1_B32) {
if (Opc == AMDGPU::S_BITSET0_B32 || Opc == AMDGPU::S_BITSET1_B32) {
Src0->ChangeToImmediate(NewImm);
// Remove the immediate and add the tied input.
MI.getOperand(2).ChangeToRegister(Dest->getReg(), /*IsDef*/ false,
Expand All @@ -594,6 +595,66 @@ bool SIShrinkInstructions::shrinkScalarLogicOp(MachineInstr &MI) const {
return false;
}

// case 1:
// From:
// s_lshl_b32 s1, 1, s1
// s_or_b32 s0, s0, s1
// To:
// s_bitset1_b32 s0, s1
//
// case 2:
// s_lshl_b32 s1, 1, s1
// s_andn2_b32 s0, s0, s1
// To:
// s_bitset0_b32 s0, s1
bool SIShrinkInstructions::shrinkToBitset(MachineInstr &MI) const {
MachineOperand *Dest = &MI.getOperand(0);
MachineOperand *Src0 = &MI.getOperand(1);
MachineOperand *Src1 = &MI.getOperand(2);

if (!Src0->isReg() || !Src1->isReg() || Dest->getReg() != Src0->getReg())
return false;

MachineInstr *Shl = MRI->getUniqueVRegDef(Src1->getReg());
if (!Shl || Shl->getOpcode() != AMDGPU::S_LSHL_B32 ||
!Shl->getOperand(1).isImm() || Shl->getOperand(1).getImm() != 1 ||
MI.getParent() != Shl->getParent())
return false;

if (!MRI->hasAtMostUserInstrs(Shl->getOperand(0).getReg(), 2))
return false;

int ShlSrc1Reg = Shl->getOperand(2).getReg();
bool IsKilled = false;
for (auto IE = MI.getIterator(), I = std::next(Shl->getIterator()); I != IE;
++I) {
for (MachineOperand &MO : I->operands()) {
if (MO.isReg() && MO.getReg() == ShlSrc1Reg) {
if (MO.isDef())
return false;
if (MO.isKill()) {
MO.setIsKill(false);
IsKilled = true;
}
}
}
}

unsigned int NewOpc = (MI.getOpcode() == AMDGPU::S_OR_B32)
? AMDGPU::S_BITSET1_B32
: AMDGPU::S_BITSET0_B32;
MI.setDesc(TII->get(NewOpc));
Src0->setReg(ShlSrc1Reg);
if (IsKilled)
Src0->setIsKill(true);
MI.getOperand(2).ChangeToRegister(Dest->getReg(), /*IsDef*/ false,
/*isImp*/ false, Src0->isKill(),
/*isDead*/ false, Src0->isUndef());
MI.tieOperands(0, 2);
Shl->eraseFromParent();
return true;
}

// This is the same as MachineInstr::readsRegister/modifiesRegister except
// it takes subregs into account.
bool SIShrinkInstructions::instAccessReg(
Expand Down Expand Up @@ -951,6 +1012,12 @@ bool SIShrinkInstructions::run(MachineFunction &MF) {
continue;
}

if (MI.getOpcode() == AMDGPU::S_ANDN2_B32 ||
MI.getOpcode() == AMDGPU::S_OR_B32) {
if (shrinkToBitset(MI))
continue;
}

if (TII->isMIMG(MI.getOpcode()) &&
ST->getGeneration() >= AMDGPUSubtarget::GFX10 &&
MF.getProperties().hasProperty(
Expand Down
27 changes: 9 additions & 18 deletions llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -728,9 +728,8 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX10W32-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10W32-NEXT: s_ff1_i32_b32 s2, s1
; GFX10W32-NEXT: v_readlane_b32 s3, v0, s2
; GFX10W32-NEXT: s_lshl_b32 s6, 1, s2
; GFX10W32-NEXT: v_writelane_b32 v1, s0, s2
; GFX10W32-NEXT: s_andn2_b32 s1, s1, s6
; GFX10W32-NEXT: s_bitset0_b32 s1, s2
; GFX10W32-NEXT: s_add_i32 s0, s0, s3
; GFX10W32-NEXT: s_cmp_lg_u32 s1, 0
; GFX10W32-NEXT: s_cbranch_scc1 .LBB2_1
Expand Down Expand Up @@ -813,9 +812,8 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX11W32-NEXT: s_ctz_i32_b32 s2, s1
; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11W32-NEXT: v_readlane_b32 s3, v1, s2
; GFX11W32-NEXT: s_lshl_b32 s6, 1, s2
; GFX11W32-NEXT: v_writelane_b32 v0, s0, s2
; GFX11W32-NEXT: s_and_not1_b32 s1, s1, s6
; GFX11W32-NEXT: s_bitset0_b32 s1, s2
; GFX11W32-NEXT: s_add_i32 s0, s0, s3
; GFX11W32-NEXT: s_cmp_lg_u32 s1, 0
; GFX11W32-NEXT: s_cbranch_scc1 .LBB2_1
Expand Down Expand Up @@ -898,9 +896,8 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: s_ctz_i32_b32 s2, s1
; GFX12W32-NEXT: s_wait_alu 0xfffe
; GFX12W32-NEXT: v_readlane_b32 s3, v1, s2
; GFX12W32-NEXT: s_lshl_b32 s6, 1, s2
; GFX12W32-NEXT: v_writelane_b32 v0, s0, s2
; GFX12W32-NEXT: s_and_not1_b32 s1, s1, s6
; GFX12W32-NEXT: s_bitset0_b32 s1, s2
; GFX12W32-NEXT: s_add_co_i32 s0, s0, s3
; GFX12W32-NEXT: s_wait_alu 0xfffe
; GFX12W32-NEXT: s_cmp_lg_u32 s1, 0
Expand Down Expand Up @@ -1120,9 +1117,8 @@ define amdgpu_kernel void @struct_add_i32_varying_vdata(ptr addrspace(1) %out, p
; GFX10W32-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10W32-NEXT: s_ff1_i32_b32 s2, s1
; GFX10W32-NEXT: v_readlane_b32 s3, v0, s2
; GFX10W32-NEXT: s_lshl_b32 s6, 1, s2
; GFX10W32-NEXT: v_writelane_b32 v1, s0, s2
; GFX10W32-NEXT: s_andn2_b32 s1, s1, s6
; GFX10W32-NEXT: s_bitset0_b32 s1, s2
; GFX10W32-NEXT: s_add_i32 s0, s0, s3
; GFX10W32-NEXT: s_cmp_lg_u32 s1, 0
; GFX10W32-NEXT: s_cbranch_scc1 .LBB3_1
Expand Down Expand Up @@ -1211,9 +1207,8 @@ define amdgpu_kernel void @struct_add_i32_varying_vdata(ptr addrspace(1) %out, p
; GFX11W32-NEXT: s_ctz_i32_b32 s2, s1
; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11W32-NEXT: v_readlane_b32 s3, v1, s2
; GFX11W32-NEXT: s_lshl_b32 s6, 1, s2
; GFX11W32-NEXT: v_writelane_b32 v0, s0, s2
; GFX11W32-NEXT: s_and_not1_b32 s1, s1, s6
; GFX11W32-NEXT: s_bitset0_b32 s1, s2
; GFX11W32-NEXT: s_add_i32 s0, s0, s3
; GFX11W32-NEXT: s_cmp_lg_u32 s1, 0
; GFX11W32-NEXT: s_cbranch_scc1 .LBB3_1
Expand Down Expand Up @@ -1301,9 +1296,8 @@ define amdgpu_kernel void @struct_add_i32_varying_vdata(ptr addrspace(1) %out, p
; GFX12W32-NEXT: s_ctz_i32_b32 s2, s1
; GFX12W32-NEXT: s_wait_alu 0xfffe
; GFX12W32-NEXT: v_readlane_b32 s3, v1, s2
; GFX12W32-NEXT: s_lshl_b32 s6, 1, s2
; GFX12W32-NEXT: v_writelane_b32 v0, s0, s2
; GFX12W32-NEXT: s_and_not1_b32 s1, s1, s6
; GFX12W32-NEXT: s_bitset0_b32 s1, s2
; GFX12W32-NEXT: s_add_co_i32 s0, s0, s3
; GFX12W32-NEXT: s_wait_alu 0xfffe
; GFX12W32-NEXT: s_cmp_lg_u32 s1, 0
Expand Down Expand Up @@ -2183,9 +2177,8 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX10W32-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10W32-NEXT: s_ff1_i32_b32 s2, s1
; GFX10W32-NEXT: v_readlane_b32 s3, v0, s2
; GFX10W32-NEXT: s_lshl_b32 s6, 1, s2
; GFX10W32-NEXT: v_writelane_b32 v1, s0, s2
; GFX10W32-NEXT: s_andn2_b32 s1, s1, s6
; GFX10W32-NEXT: s_bitset0_b32 s1, s2
; GFX10W32-NEXT: s_add_i32 s0, s0, s3
; GFX10W32-NEXT: s_cmp_lg_u32 s1, 0
; GFX10W32-NEXT: s_cbranch_scc1 .LBB7_1
Expand Down Expand Up @@ -2268,9 +2261,8 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX11W32-NEXT: s_ctz_i32_b32 s2, s1
; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX11W32-NEXT: v_readlane_b32 s3, v1, s2
; GFX11W32-NEXT: s_lshl_b32 s6, 1, s2
; GFX11W32-NEXT: v_writelane_b32 v0, s0, s2
; GFX11W32-NEXT: s_and_not1_b32 s1, s1, s6
; GFX11W32-NEXT: s_bitset0_b32 s1, s2
; GFX11W32-NEXT: s_add_i32 s0, s0, s3
; GFX11W32-NEXT: s_cmp_lg_u32 s1, 0
; GFX11W32-NEXT: s_cbranch_scc1 .LBB7_1
Expand Down Expand Up @@ -2354,9 +2346,8 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: s_ctz_i32_b32 s2, s1
; GFX12W32-NEXT: s_wait_alu 0xfffe
; GFX12W32-NEXT: v_readlane_b32 s3, v1, s2
; GFX12W32-NEXT: s_lshl_b32 s6, 1, s2
; GFX12W32-NEXT: v_writelane_b32 v0, s0, s2
; GFX12W32-NEXT: s_and_not1_b32 s1, s1, s6
; GFX12W32-NEXT: s_bitset0_b32 s1, s2
; GFX12W32-NEXT: s_add_co_i32 s0, s0, s3
; GFX12W32-NEXT: s_wait_alu 0xfffe
; GFX12W32-NEXT: s_cmp_lg_u32 s1, 0
Expand Down
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