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[SelectionDAG] Improve type legalisation for PARTIAL_REDUCE_MLA #130935

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Merged
merged 12 commits into from
May 1, 2025
Merged

[SelectionDAG] Improve type legalisation for PARTIAL_REDUCE_MLA #130935

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a27a811
[SelectionDAG] Improve type legalisation for PARTIAL_REDUCE_MLA
JamesChesterman Feb 28, 2025
4ee4990
Explicitly set PartialReduceMLAActions
NickGuy-Arm Apr 15, 2025
2ff7e91
Re-generate tests
NickGuy-Arm Apr 24, 2025
76d2744
Remove erroneous setPartialReduceMLAAction calls
NickGuy-Arm Apr 24, 2025
b36ca2b
Remove dead/duplicate code
NickGuy-Arm Apr 24, 2025
6c782ea
Address comments and alter how PARTIAL_REDUCE_MLA operands are split
NickGuy-Arm Apr 29, 2025
60b4ec6
Split only the operands if the accumulator doesn't need it.
NickGuy-Arm Apr 30, 2025
6693aa0
Remove dead code
NickGuy-Arm Apr 30, 2025
2aabffb
New test precommit
NickGuy-Arm Apr 30, 2025
b45dc07
Fix typo and update test
NickGuy-Arm Apr 30, 2025
c1c94ce
Address nits
NickGuy-Arm Apr 30, 2025
7c2ac73
Update tests
NickGuy-Arm May 1, 2025
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41 changes: 38 additions & 3 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3220,8 +3220,30 @@ void DAGTypeLegalizer::SplitVecRes_VP_REVERSE(SDNode *N, SDValue &Lo,
void DAGTypeLegalizer::SplitVecRes_PARTIAL_REDUCE_MLA(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDLoc DL(N);
SDValue Expanded = TLI.expandPartialReduceMLA(N, DAG);
std::tie(Lo, Hi) = DAG.SplitVector(Expanded, DL);
SDValue Acc = N->getOperand(0);
SDValue Input1 = N->getOperand(1);
SDValue Input2 = N->getOperand(2);

SDValue AccLo, AccHi;
std::tie(AccLo, AccHi) = DAG.SplitVector(Acc, DL);
unsigned Opcode = N->getOpcode();

// If the input types don't need splitting, just accumulate into the
// low part of the accumulator.
if (getTypeAction(Input1.getValueType()) != TargetLowering::TypeSplitVector) {
Lo = DAG.getNode(Opcode, DL, AccLo.getValueType(), AccLo, Input1, Input2);
Hi = AccHi;
return;
}

SDValue Input1Lo, Input1Hi;
SDValue Input2Lo, Input2Hi;
std::tie(Input1Lo, Input1Hi) = DAG.SplitVector(Input1, DL);
std::tie(Input2Lo, Input2Hi) = DAG.SplitVector(Input2, DL);
EVT ResultVT = AccLo.getValueType();

Lo = DAG.getNode(Opcode, DL, ResultVT, AccLo, Input1Lo, Input2Lo);
Hi = DAG.getNode(Opcode, DL, ResultVT, AccHi, Input1Hi, Input2Hi);
}

void DAGTypeLegalizer::SplitVecRes_VECTOR_DEINTERLEAVE(SDNode *N) {
Expand Down Expand Up @@ -4501,7 +4523,20 @@ SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_HISTOGRAM(SDNode *N) {
}

SDValue DAGTypeLegalizer::SplitVecOp_PARTIAL_REDUCE_MLA(SDNode *N) {
return TLI.expandPartialReduceMLA(N, DAG);
SDValue Acc = N->getOperand(0);
assert(getTypeAction(Acc.getValueType()) != TargetLowering::TypeSplitVector &&
"Accumulator should already be a legal type, and shouldn't need "
"further splitting");

SDLoc DL(N);
SDValue Input1Lo, Input1Hi, Input2Lo, Input2Hi;
std::tie(Input1Lo, Input1Hi) = DAG.SplitVector(N->getOperand(1), DL);
std::tie(Input2Lo, Input2Hi) = DAG.SplitVector(N->getOperand(2), DL);
unsigned Opcode = N->getOpcode();
EVT ResultVT = Acc.getValueType();

SDValue Lo = DAG.getNode(Opcode, DL, ResultVT, Acc, Input1Lo, Input2Lo);
return DAG.getNode(Opcode, DL, ResultVT, Lo, Input1Hi, Input2Hi);
}

//===----------------------------------------------------------------------===//
Expand Down
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