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AMDGPU: Add mir test for agpr constant reg_sequence handling #129058

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Merged
merged 2 commits into from
Mar 3, 2025
Merged

AMDGPU: Add mir test for agpr constant reg_sequence handling #129058

merged 2 commits into from
Mar 3, 2025

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@arsenm arsenm commented Feb 27, 2025

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arsenm commented Feb 27, 2025 •
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@arsenm arsenm marked this pull request as ready for review February 27, 2025 13:48
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llvmbot commented Feb 27, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

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Patch is 28.27 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/129058.diff

1 Files Affected:

  • (added) llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir (+559)
diff --git a/llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir b/llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
new file mode 100644
index 0000000000000..95112826b7112
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
@@ -0,0 +1,559 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -run-pass=si-fold-operands -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-fold-operands -o - %s | FileCheck %s
+
+---
+name: s_mov_b32_0_copy_vgpr_reg_sequence_128_splat_copy_to_agpr
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: s_mov_b32_0_copy_vgpr_reg_sequence_128_splat_copy_to_agpr
+    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[V_MOV_B32_e32_]], %subreg.sub2, [[V_MOV_B32_e32_]], %subreg.sub3
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY [[REG_SEQUENCE]]
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY]]
+    ; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+    %0:sgpr_32 = S_MOV_B32 0
+    %1:vgpr_32 = COPY killed %0
+    %2:vreg_128 = REG_SEQUENCE %1, %subreg.sub0, %1, %subreg.sub1, %1, %subreg.sub2, %1, %subreg.sub3
+    %3:areg_128 = COPY %2
+    $agpr0_agpr1_agpr2_agpr3 = COPY %3
+    S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+
+...
+
+---
+name: v_mov_b32_0_vgpr_reg_sequence_128_splat_copy_to_agpr
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: v_mov_b32_0_vgpr_reg_sequence_128_splat_copy_to_agpr
+    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[V_MOV_B32_e32_]], %subreg.sub2, [[V_MOV_B32_e32_]], %subreg.sub3
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY killed [[REG_SEQUENCE]]
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY]]
+    ; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+    %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %1:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1, %0, %subreg.sub2, %0, %subreg.sub3
+    %2:areg_128 = COPY killed %1
+    $agpr0_agpr1_agpr2_agpr3 = COPY %2
+    S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+
+...
+
+---
+name: v_mov_b32_0_vgpr_reg_sequence_128_splat_copy_to_agpr_multi_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: v_mov_b32_0_vgpr_reg_sequence_128_splat_copy_to_agpr_multi_use
+    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[V_MOV_B32_e32_]], %subreg.sub2, [[V_MOV_B32_e32_]], %subreg.sub3
+    ; CHECK-NEXT: S_NOP 0, implicit [[REG_SEQUENCE]]
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY killed [[REG_SEQUENCE]]
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY]]
+    ; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+    %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %1:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1, %0, %subreg.sub2, %0, %subreg.sub3
+    S_NOP 0, implicit %1
+    %2:areg_128 = COPY killed %1
+    $agpr0_agpr1_agpr2_agpr3 = COPY %2
+    S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+
+...
+
+---
+name: s_mov_b32_literal_copy_vgpr_reg_sequence_128_splat_copy_to_agpr
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: s_mov_b32_literal_copy_vgpr_reg_sequence_128_splat_copy_to_agpr
+    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 999, implicit $exec
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[V_MOV_B32_e32_]], %subreg.sub2, [[V_MOV_B32_e32_]], %subreg.sub3
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY [[REG_SEQUENCE]]
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY]]
+    ; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+    %0:sgpr_32 = S_MOV_B32 999
+    %1:vgpr_32 = COPY %0
+    %2:vreg_128 = REG_SEQUENCE %1, %subreg.sub0, %1, %subreg.sub1, %1, %subreg.sub2, %1, %subreg.sub3
+    %3:areg_128 = COPY %2
+    $agpr0_agpr1_agpr2_agpr3 = COPY %3
+    S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+
+...
+
+---
+name: v_mov_b32_literal_vgpr_reg_sequence_128_splat_copy_to_agpr
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: v_mov_b32_literal_vgpr_reg_sequence_128_splat_copy_to_agpr
+    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 999, implicit $exec
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[V_MOV_B32_e32_]], %subreg.sub2, [[V_MOV_B32_e32_]], %subreg.sub3
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY killed [[REG_SEQUENCE]]
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY]]
+    ; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+    %0:vgpr_32 = V_MOV_B32_e32 999, implicit $exec
+    %1:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1, %0, %subreg.sub2, %0, %subreg.sub3
+    %2:areg_128 = COPY killed %1
+    $agpr0_agpr1_agpr2_agpr3 = COPY %2
+    S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+
+...
+
+---
+name: v_mov_b32_literal_vgpr_reg_sequence_128_splat_copy_to_agpr_multi_use
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: v_mov_b32_literal_vgpr_reg_sequence_128_splat_copy_to_agpr_multi_use
+    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 999, implicit $exec
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[V_MOV_B32_e32_]], %subreg.sub2, [[V_MOV_B32_e32_]], %subreg.sub3
+    ; CHECK-NEXT: S_NOP 0, implicit [[REG_SEQUENCE]]
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY killed [[REG_SEQUENCE]]
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY]]
+    ; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+    %0:vgpr_32 = V_MOV_B32_e32 999, implicit $exec
+    %1:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1, %0, %subreg.sub2, %0, %subreg.sub3
+    S_NOP 0, implicit %1
+    %2:areg_128 = COPY killed %1
+    $agpr0_agpr1_agpr2_agpr3 = COPY %2
+    S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+
+...
+
+---
+name: s_mov_b32_0_splat_sgpr_128_copy_vgpr_copy_agpr_multi_use_reg_sequence_copy
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: s_mov_b32_0_splat_sgpr_128_copy_vgpr_copy_agpr_multi_use_reg_sequence_copy
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[S_MOV_B32_]], %subreg.sub0, killed [[S_MOV_B32_]], %subreg.sub1, killed [[S_MOV_B32_]], %subreg.sub2, killed [[S_MOV_B32_]], %subreg.sub3
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE]]
+    ; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_3:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
+    ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:areg_128 = REG_SEQUENCE [[V_ACCVGPR_WRITE_B32_e64_]], %subreg.sub0, [[V_ACCVGPR_WRITE_B32_e64_1]], %subreg.sub1, [[V_ACCVGPR_WRITE_B32_e64_2]], %subreg.sub2, [[V_ACCVGPR_WRITE_B32_e64_3]], %subreg.sub3
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[REG_SEQUENCE1]]
+    ; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+    %0:sgpr_32 = S_MOV_B32 0
+    %1:sgpr_128 = REG_SEQUENCE killed %0, %subreg.sub0, killed %0, %subreg.sub1, killed %0, %subreg.sub2, killed %0, %subreg.sub3
+    %2:vreg_128 = COPY killed %1
+    S_NOP 0, implicit %2
+    %3:areg_128 = COPY %2
+    $agpr0_agpr1_agpr2_agpr3 = COPY %3
+    S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+
+...
+
+---
+name: s_mov_b32_0_splat_sgpr_128_copy_vgpr_copy_agpr_multi_use_reg_sequence
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: s_mov_b32_0_splat_sgpr_128_copy_vgpr_copy_agpr_multi_use_reg_sequence
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1, [[S_MOV_B32_]], %subreg.sub2, [[S_MOV_B32_]], %subreg.sub3
+    ; CHECK-NEXT: S_NOP 0, implicit [[REG_SEQUENCE]]
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_3:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
+    ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:areg_128 = REG_SEQUENCE [[V_ACCVGPR_WRITE_B32_e64_]], %subreg.sub0, [[V_ACCVGPR_WRITE_B32_e64_1]], %subreg.sub1, [[V_ACCVGPR_WRITE_B32_e64_2]], %subreg.sub2, [[V_ACCVGPR_WRITE_B32_e64_3]], %subreg.sub3
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[REG_SEQUENCE1]]
+    ; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+    %0:sgpr_32 = S_MOV_B32 0
+    %1:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1, %0, %subreg.sub2, %0, %subreg.sub3
+    S_NOP 0, implicit %1
+    %2:vreg_128 = COPY %1
+    %3:areg_128 = COPY %2
+    $agpr0_agpr1_agpr2_agpr3 = COPY %3
+    S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+
+...
+
+---
+name: s_mov_b32_0_splat_sgpr_128_copy_vgpr_copy_agpr
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: s_mov_b32_0_splat_sgpr_128_copy_vgpr_copy_agpr
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_3:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128 = REG_SEQUENCE [[V_ACCVGPR_WRITE_B32_e64_]], %subreg.sub0, [[V_ACCVGPR_WRITE_B32_e64_1]], %subreg.sub1, [[V_ACCVGPR_WRITE_B32_e64_2]], %subreg.sub2, [[V_ACCVGPR_WRITE_B32_e64_3]], %subreg.sub3
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[REG_SEQUENCE]]
+    ; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+    %0:sgpr_32 = S_MOV_B32 0
+    %1:sgpr_128 = REG_SEQUENCE killed %0, %subreg.sub0, killed %0, %subreg.sub1, killed %0, %subreg.sub2, killed %0, %subreg.sub3
+    %2:vreg_128 = COPY %1
+    %3:areg_128 = COPY %2
+    $agpr0_agpr1_agpr2_agpr3 = COPY %3
+    S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+
+...
+
+---
+name: s_mov_b32_999_splat_sgpr_128_copy_vgpr_copy_agpr
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: s_mov_b32_999_splat_sgpr_128_copy_vgpr_copy_agpr
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 999
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_3:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128 = REG_SEQUENCE [[V_ACCVGPR_WRITE_B32_e64_]], %subreg.sub0, [[V_ACCVGPR_WRITE_B32_e64_1]], %subreg.sub1, [[V_ACCVGPR_WRITE_B32_e64_2]], %subreg.sub2, [[V_ACCVGPR_WRITE_B32_e64_3]], %subreg.sub3
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[REG_SEQUENCE]]
+    ; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+    %0:sgpr_32 = S_MOV_B32 999
+    %1:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1, %0, %subreg.sub2, %0, %subreg.sub3
+    %2:vreg_128 = COPY %1
+    %3:areg_128 = COPY %2
+    $agpr0_agpr1_agpr2_agpr3 = COPY %3
+    S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+
+...
+
+---
+name: s_mov_b32_mixed_imm_literal_inputs_splat_sgpr_128_copy_vgpr_copy_agpr
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: s_mov_b32_mixed_imm_literal_inputs_splat_sgpr_128_copy_vgpr_copy_agpr
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 999
+    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 1
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 1, implicit $exec
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[COPY]], implicit $exec
+    ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_3:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 1, implicit $exec
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128 = REG_SEQUENCE [[V_ACCVGPR_WRITE_B32_e64_]], %subreg.sub0, [[V_ACCVGPR_WRITE_B32_e64_1]], %subreg.sub1, [[V_ACCVGPR_WRITE_B32_e64_2]], %subreg.sub2, [[V_ACCVGPR_WRITE_B32_e64_3]], %subreg.sub3
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[REG_SEQUENCE]]
+    ; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+    %0:sgpr_32 = S_MOV_B32 999
+    %1:sgpr_32 = S_MOV_B32 1
+    %2:sgpr_128 = REG_SEQUENCE %1, %subreg.sub0, %0, %subreg.sub1, %0, %subreg.sub2, %1, %subreg.sub3
+    %3:vreg_128 = COPY %2
+    %4:areg_128 = COPY %3
+    $agpr0_agpr1_agpr2_agpr3 = COPY %4
+    S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+
+...
+
+---
+name: s_mov_b32_0_splat_sgpr_128_copy_agpr
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: s_mov_b32_0_splat_sgpr_128_copy_agpr
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1, [[S_MOV_B32_]], %subreg.sub2, [[S_MOV_B32_]], %subreg.sub3
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY [[REG_SEQUENCE]]
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY]]
+    ; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+    %0:sgpr_32 = S_MOV_B32 0
+    %1:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1, %0, %subreg.sub2, %0, %subreg.sub3
+    %2:areg_128 = COPY %1
+    $agpr0_agpr1_agpr2_agpr3 = COPY %2
+    S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+
+...
+
+---
+name: v_mov_b32_mixed_literal_imm_inputs_vgpr_reg_sequence_128_splat_copy_to_agpr
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: v_mov_b32_mixed_literal_imm_inputs_vgpr_reg_sequence_128_splat_copy_to_agpr
+    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 999, implicit $exec
+    ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 8, implicit $exec
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1, [[V_MOV_B32_e32_2]], %subreg.sub2, [[V_MOV_B32_e32_1]], %subreg.sub3
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY killed [[REG_SEQUENCE]]
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY]]
+    ; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+    %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %1:vgpr_32 = V_MOV_B32_e32 999, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_e32 8, implicit $exec
+    %3:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %1, %subreg.sub3
+    %4:areg_128 = COPY killed %3
+    $agpr0_agpr1_agpr2_agpr3 = COPY %4
+    S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+
+...
+
+---
+name: s_mov_b64_0_copy_vgpr_reg_sequence_128_splat_copy_to_agpr_elt64
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: s_mov_b64_0_copy_vgpr_reg_sequence_128_splat_copy_to_agpr_elt64
+    ; CHECK: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[V_MOV_B]], %subreg.sub0_sub1, [[V_MOV_B]], %subreg.sub2_sub3
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY [[REG_SEQUENCE]]
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY]]
+    ; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+    %0:sreg_64 = S_MOV_B64 0
+    %1:vreg_64_align2 = COPY killed %0
+    %2:vreg_128 = REG_SEQUENCE %1, %subreg.sub0_sub1, %1, %subreg.sub2_sub3
+    %3:areg_128 = COPY %2
+    $agpr0_agpr1_agpr2_agpr3 = COPY %3
+    S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+
+...
+
+---
+name: s_mov_b64_0_copy_vgpr_reg_sequence_128_splat_copy_to_agpr_subreg_elt32
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: s_mov_b64_0_copy_vgpr_reg_sequence_128_splat_copy_to_agpr_subreg_elt32
+    ; CHECK: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[V_MOV_B]].sub0, %subreg.sub0, [[V_MOV_B]].sub1, %subreg.sub1, [[V_MOV_B]], %subreg.sub1_sub2
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY [[REG_SEQUENCE]]
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY]]
+    ; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+    %0:sreg_64 = S_MOV_B64 0
+    %1:vreg_64_align2 = COPY killed %0
+    %2:vreg_128 = REG_SEQUENCE %1.sub0, %subreg.sub0, %1.sub1, %subreg.sub1, %1, %subreg.sub1_sub2
+    %3:areg_128 = COPY %2
+    $agpr0_agpr1_agpr2_agpr3 = COPY %3
+    S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+
+...
+
+---
+name: s_mov_b64_plus_unfoldable_copy_vgpr_reg_sequence_128_splat_copy_to_agpr_elt64
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: s_mov_b64_plus_unfoldable_copy_vgpr_reg_sequence_128_splat_copy_to_agpr_elt64
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 0, implicit $exec
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[V_MOV_B]], %subreg.sub0_sub1, [[COPY]], %subreg.sub2_sub3
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_128 = COPY [[REG_SEQUENCE]]
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY1]]
+    ; CHECK-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+    %0:sreg_64 = S_MOV_B64 0
+    %1:vreg_64_align2 = COPY killed %0
+    %2:vreg_64_align2 = COPY $vgpr0_vgpr1
+    %3:vreg_128 = REG_SEQUENCE %1, %subreg.sub0_sub1, %2, %subreg.sub2_sub3
+    %4:areg_128 = COPY %3
+    $agpr0_agpr1_agpr2_agpr3 = COPY %4
+    S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3
+
+...
+
+---
+name: sgpr_source_copy_vgpr_reg_sequence_128_splat_copy_to_agpr_elt64
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr8_sgpr9
+    ; CHECK-LABEL: name: sgpr_source_copy_vgpr_reg_sequence_128_splat_copy_to_agpr_elt64
+    ; CHECK: liveins: $sgpr8_sgpr9
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY killed [[COPY]]
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:areg_128 = COPY [[REG_SEQUENCE]]
+    ; CHECK-NEXT: $agpr0_agpr1_agpr2_agpr3 = COPY [[COPY2]]
+   ...
[truncated]

@arsenm arsenm force-pushed the users/arsenm/add-tests-agpr-reg-sequence-fold branch from 3fe0c48 to a20c838 Compare February 27, 2025 15:38
@arsenm arsenm force-pushed the users/arsenm/amdgpu/factor-copy-chain-lookup-func branch from d3d3005 to 0d18d8c Compare February 27, 2025 15:39
Base automatically changed from users/arsenm/amdgpu/factor-copy-chain-lookup-func to main February 27, 2025 17:50
rampitec
rampitec reviewed Feb 27, 2025
View reviewed changes
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp Outdated
@@ -781,6 +781,27 @@ bool SIFoldOperandsImpl::isUseSafeToFold(const MachineInstr &MI,
return !TII->isSDWA(MI);
}

static MachineOperand *lookUpCopyChain(const SIInstrInfo &TII,
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It does more than adding test. Needs restacking?

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yes

@arsenm arsenm force-pushed the users/arsenm/add-tests-agpr-reg-sequence-fold branch from a20c838 to 60ac34e Compare March 3, 2025 03:02
This was referenced Mar 3, 2025
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arsenm commented Mar 3, 2025 •
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Merge activity

  • Mar 3, 4:13 AM EST: A user started a stack merge that includes this pull request via Graphite.
  • Mar 3, 4:16 AM EST: Graphite rebased this pull request as part of a merge.
  • Mar 3, 4:19 AM EST: A user merged this pull request with Graphite.

@arsenm arsenm force-pushed the users/arsenm/add-tests-agpr-reg-sequence-fold branch from 60ac34e to da35f84 Compare March 3, 2025 09:15
@arsenm arsenm merged commit 7be8b78 into main Mar 3, 2025
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@arsenm arsenm deleted the users/arsenm/add-tests-agpr-reg-sequence-fold branch March 3, 2025 09:19
jph-13 pushed a commit to jph-13/llvm-project that referenced this pull request Mar 21, 2025
@arsenm @jph-13
AMDGPU: Add mir test for agpr constant reg_sequence handling (llvm#12…
833fd4c 
…9058)
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