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[AMDGPU] SelectionDAG support for vector type set 0 to multiple sgpr64 #128017

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[AMDGPU] SelectionDAG support for vector type set 0 to multiple sgpr64 #128017

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55 changes: 55 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -634,6 +634,61 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) {
case ISD::BUILD_VECTOR: {
EVT VT = N->getValueType(0);
unsigned NumVectorElts = VT.getVectorNumElements();

auto IsSplatAllZeros = [this](SDNode *N) -> bool {
if (ISD::isConstantSplatVectorAllZeros(N))
return true;

// Types may have legalized by stripping the 16 bit multi-element vector
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It would be better to adjust the legalizer to do this in the first place

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As in, allow vector types as long as they splat 0?

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Even if they don't splat 0

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The splatness isn't significant, and if we're going to have 64-bit vector elements we should have made them legal throughout the DAG, not just during selection

// into multiple BUILD_VECTORs. Peek through and see if it is all zeros
// regardless of what the legalizer did. Assumes cases along the lines of:
// v8i16 build_vector 0, 0, 0, 0, 0, 0, 0, 0
// -> legalizer ->
// t0 = v2i16 build_vector 0, 0
// t1 = bitcast t0 to i32
// v4i32 build_vector t1, t1, t1, t1
if (CurDAG->isSplatValue(SDValue(N, 0))) {
SDValue Op = peekThroughBitcasts(N->getOperand(0));
EVT InnerVT = Op.getValueType();
if (InnerVT.isVector() && Op.getOpcode() == ISD::BUILD_VECTOR &&
InnerVT.getVectorNumElements() == 2)
return ISD::isConstantSplatVectorAllZeros(Op.getNode());
}
return false;
};
if (IsSplatAllZeros(N)) {
unsigned FixedBitSize = VT.getFixedSizeInBits();
SDLoc DL(N);
if (FixedBitSize == 64) {
SDValue Set0 = {
CurDAG->getMachineNode(AMDGPU::S_MOV_B64_IMM_PSEUDO, DL, MVT::i64,
CurDAG->getTargetConstant(0, DL, MVT::i64)),
0};
CurDAG->SelectNodeTo(N, AMDGPU::COPY, VT, Set0);
return;
} else if (NumVectorElts <= 32 && (FixedBitSize % 64 == 0)) {
SmallVector<SDValue, 32 * 2 + 1> Ops((FixedBitSize / 64) * 2 + 1);
SDValue Set0 = {
CurDAG->getMachineNode(AMDGPU::S_MOV_B64_IMM_PSEUDO, DL, MVT::i64,
CurDAG->getTargetConstant(0, DL, MVT::i64)),
0};
unsigned RCID =
SIRegisterInfo::getSGPRClassForBitWidth(FixedBitSize)->getID();
Ops[0] = CurDAG->getTargetConstant(RCID, DL, MVT::i32);

for (unsigned i = 0, CurrentBitSize = FixedBitSize; CurrentBitSize != 0;
++i, CurrentBitSize -= 64) {
unsigned SubRegs =
SIRegisterInfo::getSubRegFromChannel(i * 2, /*NumRegs=*/2);
Ops[i * 2 + 1] = Set0;
Ops[i * 2 + 2] = CurDAG->getTargetConstant(SubRegs, DL, MVT::i32);
}

CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, VT, Ops);
return;
}
}

if (VT.getScalarSizeInBits() == 16) {
if (Opc == ISD::BUILD_VECTOR && NumVectorElts == 2) {
if (SDNode *Packed = packConstantV2I16(N, *CurDAG)) {
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17 changes: 8 additions & 9 deletions llvm/test/CodeGen/AMDGPU/adjust-writemask-cse.ll
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Expand Up @@ -4,15 +4,14 @@
define float @test() {
; GFX10-LABEL: name: test
; GFX10: bb.0.bb:
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_256 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1, [[S_MOV_B32_]], %subreg.sub2, [[S_MOV_B32_]], %subreg.sub3, [[S_MOV_B32_]], %subreg.sub4, [[S_MOV_B32_]], %subreg.sub5, [[S_MOV_B32_]], %subreg.sub6, [[S_MOV_B32_]], %subreg.sub7
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX10-NEXT: [[IMAGE_LOAD_V2_V2_nsa_gfx10_:%[0-9]+]]:vreg_64 = IMAGE_LOAD_V2_V2_nsa_gfx10 [[COPY]], [[COPY1]], killed [[REG_SEQUENCE]], 3, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s96), align 16, addrspace 8)
; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[IMAGE_LOAD_V2_V2_nsa_gfx10_]].sub1
; GFX10-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[IMAGE_LOAD_V2_V2_nsa_gfx10_]].sub0
; GFX10-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY2]], 0, killed [[COPY3]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: [[V_ADD_F32_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, killed [[V_ADD_F32_e64_]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 0
; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_256 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[S_MOV_B64_]], %subreg.sub2_sub3, [[S_MOV_B64_]], %subreg.sub4_sub5, [[S_MOV_B64_]], %subreg.sub6_sub7
; GFX10-NEXT: [[V_MOV_B32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0
; GFX10-NEXT: [[IMAGE_LOAD_V2_V2_nsa_gfx10_:%[0-9]+]]:vreg_64 = IMAGE_LOAD_V2_V2_nsa_gfx10 [[V_MOV_B32_]], [[V_MOV_B32_]], killed [[REG_SEQUENCE]], 3, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s96), align 16, addrspace 8)
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[IMAGE_LOAD_V2_V2_nsa_gfx10_]].sub1
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[IMAGE_LOAD_V2_V2_nsa_gfx10_]].sub0
; GFX10-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 0, killed [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: [[V_ADD_F32_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, killed [[V_ADD_F32_e64_]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: $vgpr0 = COPY [[V_ADD_F32_e64_1]]
; GFX10-NEXT: SI_RETURN implicit $vgpr0
bb:
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