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merged 2 commits into from
Feb 18, 2025
Merged

[CodeGen] Use getSignedConstant() in more places #127501

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45e3c8d
[CodeGen] Use getSignedConstant() in more places
nikic Feb 17, 2025
a32c428
Also update one target constant case
nikic Feb 17, 2025
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20 changes: 11 additions & 9 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Expand Up @@ -11780,8 +11780,9 @@ SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
if (Align && *Align > MinSlotSize) {
VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
DAG.getConstant(Align->value() - 1, DL, PtrVT));
VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList,
DAG.getConstant(-(int64_t)Align->value(), DL, PtrVT));
VAList =
DAG.getNode(ISD::AND, DL, PtrVT, VAList,
DAG.getSignedConstant(-(int64_t)Align->value(), DL, PtrVT));
}

Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
Expand Down Expand Up @@ -16147,8 +16148,9 @@ AArch64TargetLowering::LowerWindowsDYNAMIC_STACKALLOC(SDValue Op,
Chain = SP.getValue(1);
SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size);
if (Align)
SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
DAG.getConstant(-(uint64_t)Align->value(), dl, VT));
SP =
DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
DAG.getSignedConstant(-(uint64_t)Align->value(), dl, VT));
Chain = DAG.getCopyToReg(Chain, dl, AArch64::SP, SP);
SDValue Ops[2] = {SP, Chain};
return DAG.getMergeValues(Ops, dl);
Expand Down Expand Up @@ -16185,7 +16187,7 @@ AArch64TargetLowering::LowerWindowsDYNAMIC_STACKALLOC(SDValue Op,
SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size);
if (Align)
SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
DAG.getConstant(-(uint64_t)Align->value(), dl, VT));
DAG.getSignedConstant(-(uint64_t)Align->value(), dl, VT));
Chain = DAG.getCopyToReg(Chain, dl, AArch64::SP, SP);

Chain = DAG.getCALLSEQ_END(Chain, 0, 0, SDValue(), dl);
Expand Down Expand Up @@ -16213,7 +16215,7 @@ AArch64TargetLowering::LowerInlineDYNAMIC_STACKALLOC(SDValue Op,
SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size);
if (Align)
SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
DAG.getConstant(-(uint64_t)Align->value(), dl, VT));
DAG.getSignedConstant(-(uint64_t)Align->value(), dl, VT));

// Set the real SP to the new value with a probing loop.
Chain = DAG.getNode(AArch64ISD::PROBED_ALLOCA, dl, MVT::Other, Chain, SP);
Expand Down Expand Up @@ -21485,7 +21487,7 @@ static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {

if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) {
Op = DAG.getNode(Opcode, dl, VT, Op,
DAG.getConstant(-ShiftAmount, dl, MVT::i32));
DAG.getSignedConstant(-ShiftAmount, dl, MVT::i32));
if (N->getValueType(0) == MVT::i64)
Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Op,
DAG.getConstant(0, dl, MVT::i64));
Expand Down Expand Up @@ -27364,10 +27366,10 @@ static void ReplaceATOMIC_LOAD_128Results(SDNode *N,
SDLoc dl(Val128);
Val2x64.first =
DAG.getNode(ISD::XOR, dl, MVT::i64,
DAG.getConstant(-1ULL, dl, MVT::i64), Val2x64.first);
DAG.getAllOnesConstant(dl, MVT::i64), Val2x64.first);
Val2x64.second =
DAG.getNode(ISD::XOR, dl, MVT::i64,
DAG.getConstant(-1ULL, dl, MVT::i64), Val2x64.second);
DAG.getAllOnesConstant(dl, MVT::i64), Val2x64.second);
}

SDValue Ops[] = {Val2x64.first, Val2x64.second, Ptr, Chain};
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIInstrInfo.td
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Expand Up @@ -913,7 +913,7 @@ class VGPRImm <dag frag> : PatLeaf<frag, [{
}

def NegateImm : SDNodeXForm<imm, [{
return CurDAG->getConstant(-N->getSExtValue(), SDLoc(N), MVT::i32);
return CurDAG->getSignedConstant(-N->getSExtValue(), SDLoc(N), MVT::i32);
}]>;

// TODO: When FP inline imm values work?
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
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Expand Up @@ -20786,9 +20786,9 @@ ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Chain = SP.getValue(1);
SP = DAG.getNode(ISD::SUB, DL, MVT::i32, SP, Size);
if (Align)
SP =
DAG.getNode(ISD::AND, DL, MVT::i32, SP.getValue(0),
DAG.getConstant(-(uint64_t)Align->value(), DL, MVT::i32));
SP = DAG.getNode(
ISD::AND, DL, MVT::i32, SP.getValue(0),
DAG.getSignedConstant(-(uint64_t)Align->value(), DL, MVT::i32));
Chain = DAG.getCopyToReg(Chain, DL, ARM::SP, SP);
SDValue Ops[2] = { SP, Chain };
return DAG.getMergeValues(Ops, DL);
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
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Expand Up @@ -617,7 +617,8 @@ void HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(Shl2_1)) {
int32_t ValConst = 1 << (ShlConst + C2->getSExtValue());
if (isInt<9>(-ValConst)) {
SDValue Val = CurDAG->getTargetConstant(-ValConst, dl, MVT::i32);
SDValue Val =
CurDAG->getSignedTargetConstant(-ValConst, dl, MVT::i32);
SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
MVT::i32, Shl2_0, Val);
ReplaceNode(N, Result);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
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Expand Up @@ -3491,7 +3491,7 @@ HexagonTargetLowering::PerformDAGCombine(SDNode *N,
SDValue P = Op.getOperand(0);
switch (P.getOpcode()) {
case HexagonISD::PTRUE:
return DCI.DAG.getConstant(-1, dl, ty(Op));
return DCI.DAG.getAllOnesConstant(dl, ty(Op));
case HexagonISD::PFALSE:
return getZero(dl, ty(Op), DCI.DAG);
default:
Expand Down
18 changes: 9 additions & 9 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Expand Up @@ -8883,8 +8883,8 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
Round, DAG.getConstant(2047, dl, MVT::i64));
Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
Round = DAG.getNode(ISD::AND, dl, MVT::i64,
Round, DAG.getConstant(-2048, dl, MVT::i64));
Round = DAG.getNode(ISD::AND, dl, MVT::i64, Round,
DAG.getSignedConstant(-2048, dl, MVT::i64));

// However, we cannot use that value unconditionally: if the magnitude
// of the input value is small, the bit-twiddling we did above might
Expand Down Expand Up @@ -9244,7 +9244,7 @@ SDValue PPCTargetLowering::LowerGET_ROUNDING(SDValue Op,

SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
unsigned BitWidth = VT.getSizeInBits();
uint64_t BitWidth = VT.getSizeInBits();
SDLoc dl(Op);
assert(Op.getNumOperands() == 3 &&
VT == Op.getOperand(1).getValueType() &&
Expand All @@ -9263,7 +9263,7 @@ SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
DAG.getConstant(-BitWidth, dl, AmtVT));
DAG.getSignedConstant(-BitWidth, dl, AmtVT));
SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
Expand All @@ -9274,7 +9274,7 @@ SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
SDLoc dl(Op);
unsigned BitWidth = VT.getSizeInBits();
uint64_t BitWidth = VT.getSizeInBits();
assert(Op.getNumOperands() == 3 &&
VT == Op.getOperand(1).getValueType() &&
"Unexpected SRL!");
Expand All @@ -9292,7 +9292,7 @@ SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
DAG.getConstant(-BitWidth, dl, AmtVT));
DAG.getSignedConstant(-BitWidth, dl, AmtVT));
SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
Expand All @@ -9303,7 +9303,7 @@ SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
SDLoc dl(Op);
EVT VT = Op.getValueType();
unsigned BitWidth = VT.getSizeInBits();
uint64_t BitWidth = VT.getSizeInBits();
assert(Op.getNumOperands() == 3 &&
VT == Op.getOperand(1).getValueType() &&
"Unexpected SRA!");
Expand All @@ -9320,7 +9320,7 @@ SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
DAG.getConstant(-BitWidth, dl, AmtVT));
DAG.getSignedConstant(-BitWidth, dl, AmtVT));
SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT),
Expand Down Expand Up @@ -18308,7 +18308,7 @@ static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG,
SDValue AddOrZ = NegConstant != 0 ? Add : Z;
SDValue Addc =
DAG.getNode(ISD::UADDO_CARRY, DL, DAG.getVTList(MVT::i64, CarryType),
AddOrZ, DAG.getConstant(-1ULL, DL, MVT::i64),
AddOrZ, DAG.getAllOnesConstant(DL, MVT::i64),
DAG.getConstant(0, DL, CarryType));
return DAG.getNode(ISD::UADDO_CARRY, DL, VTs, LHS,
DAG.getConstant(0, DL, MVT::i64),
Expand Down
12 changes: 7 additions & 5 deletions llvm/lib/Target/VE/VEISelLowering.cpp
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Expand Up @@ -1216,8 +1216,9 @@ SDValue VETargetLowering::lowerATOMIC_SWAP(SDValue Op,
SDValue NewVal = prepareTS1AM(Op, DAG, Flag, Bits);

SDValue Ptr = N->getOperand(1);
SDValue Aligned = DAG.getNode(ISD::AND, DL, Ptr.getValueType(),
{Ptr, DAG.getConstant(-4, DL, MVT::i64)});
SDValue Aligned =
DAG.getNode(ISD::AND, DL, Ptr.getValueType(),
{Ptr, DAG.getSignedConstant(-4, DL, MVT::i64)});
SDValue TS1AM = DAG.getAtomic(VEISD::TS1AM, DL, N->getMemoryVT(),
DAG.getVTList(Op.getNode()->getValueType(0),
Op.getNode()->getValueType(1)),
Expand All @@ -1235,8 +1236,9 @@ SDValue VETargetLowering::lowerATOMIC_SWAP(SDValue Op,
SDValue NewVal = prepareTS1AM(Op, DAG, Flag, Bits);

SDValue Ptr = N->getOperand(1);
SDValue Aligned = DAG.getNode(ISD::AND, DL, Ptr.getValueType(),
{Ptr, DAG.getConstant(-4, DL, MVT::i64)});
SDValue Aligned =
DAG.getNode(ISD::AND, DL, Ptr.getValueType(),
{Ptr, DAG.getSignedConstant(-4, DL, MVT::i64)});
SDValue TS1AM = DAG.getAtomic(VEISD::TS1AM, DL, N->getMemoryVT(),
DAG.getVTList(Op.getNode()->getValueType(0),
Op.getNode()->getValueType(1)),
Expand Down Expand Up @@ -1601,7 +1603,7 @@ SDValue VETargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
DAG.getConstant(Align - 1, DL, PtrVT));
VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList,
DAG.getConstant(-Align, DL, PtrVT));
DAG.getSignedConstant(-Align, DL, PtrVT));
// Increment the pointer, VAList, by 16 to the next vaarg.
NextPtr =
DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getIntPtrConstant(16, DL));
Expand Down
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