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release/20.x: AMDGPU: Handle gfx950 XDL-write-VGPR-VALU-Mem-Exp wait state change (#126727) #126776

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Merged
merged 1 commit into from
Feb 11, 2025
Merged

release/20.x: AMDGPU: Handle gfx950 XDL-write-VGPR-VALU-Mem-Exp wait state change (#126727) #126776

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17 changes: 10 additions & 7 deletions llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2613,12 +2613,14 @@ static int GFX940_XDL_N_PassWriteVgprVALUWawWaitStates(int NumPasses) {
return NumPasses + 3;
}

static int GFX940_XDL_N_PassWriteVgprVALUMemExpReadWaitStates(int NumPasses) {
// 2 pass -> 5
// 4 pass -> 7
// 8 pass -> 11
// 16 pass -> 19
return NumPasses + 3;
static int GFX940_XDL_N_PassWriteVgprVALUMemExpReadWaitStates(int NumPasses,
bool IsGFX950) {
// xdl def cycles | gfx940 | gfx950
// 2 pass | 5 5
// 4 pass | 7 8
// 8 pass | 11 12
// 16 pass | 19 20
return NumPasses + 3 + (NumPasses != 2 && IsGFX950);
}

static int GFX940_SMFMA_N_PassWriteVgprVALUMemExpReadWaitStates(int NumPasses) {
Expand Down Expand Up @@ -2769,7 +2771,8 @@ int GCNHazardRecognizer::checkMAIVALUHazards(MachineInstr *MI) {
} else if (ST.hasGFX940Insts()) {
NeedWaitStates =
isXDL(ST, *MFMA)
? GFX940_XDL_N_PassWriteVgprVALUMemExpReadWaitStates(NumPasses)
? GFX940_XDL_N_PassWriteVgprVALUMemExpReadWaitStates(
NumPasses, ST.hasGFX950Insts())
: GFX940_SMFMA_N_PassWriteVgprVALUMemExpReadWaitStates(
NumPasses);
} else {
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16(<8 x bfloat> %arg0, <8 x
; GCN-NEXT: v_mov_b32_e32 v9, s17
; GCN-NEXT: v_mov_b32_e32 v10, s18
; GCN-NEXT: v_mov_b32_e32 v11, s19
; GCN-NEXT: s_nop 3
; GCN-NEXT: s_nop 4
; GCN-NEXT: global_store_dwordx4 v[12:13], a[28:31], off sc0 sc1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: global_store_dwordx4 v[14:15], a[24:27], off sc0 sc1
Expand Down Expand Up @@ -122,7 +122,7 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__flags(<8 x bfloat> %arg0
; GCN-NEXT: v_mov_b32_e32 v9, s17
; GCN-NEXT: v_mov_b32_e32 v10, s18
; GCN-NEXT: v_mov_b32_e32 v11, s19
; GCN-NEXT: s_nop 3
; GCN-NEXT: s_nop 4
; GCN-NEXT: global_store_dwordx4 v[12:13], a[28:31], off sc0 sc1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: global_store_dwordx4 v[14:15], a[24:27], off sc0 sc1
Expand Down Expand Up @@ -179,7 +179,7 @@ define <16 x float> @test_mfma_f32_32x32x16_bf16__mac(<8 x bfloat> %arg0, <8 x b
; GCN-NEXT: s_nop 1
; GCN-NEXT: v_mfma_f32_32x32x16_bf16 a[0:15], v[0:3], v[4:7], a[0:15]
; GCN-NEXT: s_nop 7
; GCN-NEXT: s_nop 2
; GCN-NEXT: s_nop 3
; GCN-NEXT: v_accvgpr_read_b32 v0, a0
; GCN-NEXT: v_accvgpr_read_b32 v1, a1
; GCN-NEXT: v_accvgpr_read_b32 v2, a2
Expand Down Expand Up @@ -224,7 +224,7 @@ define <16 x float> @test_mfma_f32_32x32x16_bf16__mac__flags(<8 x bfloat> %arg0,
; GCN-NEXT: s_nop 1
; GCN-NEXT: v_mfma_f32_32x32x16_bf16 a[0:15], v[0:3], v[4:7], a[0:15] cbsz:1 abid:1 blgp:1
; GCN-NEXT: s_nop 7
; GCN-NEXT: s_nop 2
; GCN-NEXT: s_nop 3
; GCN-NEXT: v_accvgpr_read_b32 v0, a0
; GCN-NEXT: v_accvgpr_read_b32 v1, a1
; GCN-NEXT: v_accvgpr_read_b32 v2, a2
Expand Down Expand Up @@ -417,7 +417,7 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd_mac(<8 x bfloat>
; GCN-NEXT: v_mfma_f32_32x32x16_bf16 a[0:15], v[0:3], v[4:7], a[0:15]
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_nop 7
; GCN-NEXT: s_nop 1
; GCN-NEXT: s_nop 2
; GCN-NEXT: global_store_dwordx4 v0, a[12:15], s[0:1] offset:48
; GCN-NEXT: global_store_dwordx4 v0, a[8:11], s[0:1] offset:32
; GCN-NEXT: global_store_dwordx4 v0, a[4:7], s[0:1] offset:16
Expand Down Expand Up @@ -459,7 +459,7 @@ define amdgpu_kernel void @test_mfma_f32_32x32x16_bf16__vgprcd_mac_flags(<8 x bf
; GCN-NEXT: v_mfma_f32_32x32x16_bf16 a[0:15], v[0:3], v[4:7], a[0:15] cbsz:3 abid:2 blgp:1
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_nop 7
; GCN-NEXT: s_nop 1
; GCN-NEXT: s_nop 2
; GCN-NEXT: global_store_dwordx4 v0, a[12:15], s[0:1] offset:48
; GCN-NEXT: global_store_dwordx4 v0, a[8:11], s[0:1] offset:32
; GCN-NEXT: global_store_dwordx4 v0, a[4:7], s[0:1] offset:16
Expand Down
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