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[AArch64] Neoverse V1 scheduling info #126707

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1a5ef75
[AArch64] Neoverse V1 scheduling model
JulienVillette Jan 29, 2024
9941e55
[AArch64] Neoverse V1 scheduling
JulienVillette Jan 20, 2025
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1,395 changes: 797 additions & 598 deletions llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
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43 changes: 43 additions & 0 deletions llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
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Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,38 @@ def NeoverseNoLSL : MCSchedPredicate<
CheckAll<[CheckShiftLSL,
CheckShiftBy0]>>;

def Check32Ext : CheckAny<[CheckExtUXTB,
CheckExtUXTH,
CheckExtUXTX,
CheckExtSXTB,
CheckExtSXTH,
CheckExtSXTW,
CheckExtSXTX]>;

def Check64Ext : CheckAny<[CheckExtUXTB,
CheckExtUXTH,
CheckExtUXTW,
CheckExtSXTB,
CheckExtSXTH,
CheckExtSXTW,
CheckExtSXTX]>;

// Identify arithmetic instructions with an extended register.
def RegExtendAndShiftFn : TIIPredicate<"hasExtendAndShiftReg",
MCOpcodeSwitchStatement<
[MCOpcodeSwitchCase<
IsArith64ExtOp.ValidOpcodes,
MCReturnStatement<
CheckAll<[
Check64Ext,
CheckAny<[
CheckExtBy1,
CheckExtBy2,
CheckExtBy3,
CheckExtBy4]>]>>>],
MCReturnStatement<FalsePred>>>;
def RegExtendAndShiftPred : MCSchedPredicate<RegExtendAndShiftFn>;

// Identify LDR/STR H/Q-form scaled (and potentially extended) FP instructions
def NeoverseHQForm : MCSchedPredicate<
CheckAll<[
Expand Down Expand Up @@ -82,3 +114,14 @@ def NeoverseZeroMove : MCSchedPredicate<
CheckAll<[CheckOpcode<[MOVID, MOVIv2d_ns]>,
CheckImmOperand<1, 0>]>
]>>;

// Identify a load or store using the register offset addressing mode
// with a scaled register.
def NeoverseScaledIdxFn : TIIPredicate<"isNeoverseScaledAddr",
MCOpcodeSwitchStatement<
[MCOpcodeSwitchCase<
IsLoadStoreRegOffsetOp.ValidOpcodes,
MCReturnStatement<
CheckAny<[CheckMemScaled]>>>],
MCReturnStatement<FalsePred>>>;
def NeoverseScaledIdxPred : MCSchedPredicate<NeoverseScaledIdxFn>;
34 changes: 31 additions & 3 deletions llvm/lib/Target/AArch64/AArch64SchedPredicates.td
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Expand Up @@ -26,7 +26,7 @@ let FunctionMapper = "AArch64_AM::getArithExtendType" in {
}

// Check for shifting in extended arithmetic instructions.
foreach I = {0-3} in {
foreach I = {0-4} in {
let FunctionMapper = "AArch64_AM::getArithShiftValue" in
def CheckExtBy#I : CheckImmOperand<3, I>;
}
Expand Down Expand Up @@ -91,11 +91,17 @@ def CheckQForm : CheckFunctionPredicateWithTII<
>;

// Identify arithmetic instructions with extend.
def IsArithExtOp : CheckOpcode<[ADDWrx, ADDXrx, ADDSWrx, ADDSXrx,
SUBWrx, SUBXrx, SUBSWrx, SUBSXrx,
def IsArith32ExtOp : CheckOpcode<[ADDWrx, ADDSWrx,
SUBWrx, SUBSWrx]>;

def IsArith64ExtOp : CheckOpcode<[ADDXrx, ADDSXrx,
SUBXrx, SUBSXrx,
ADDXrx64, ADDSXrx64,
SUBXrx64, SUBSXrx64]>;

def IsArithExtOp : CheckOpcode<!listconcat(IsArith32ExtOp.ValidOpcodes,
IsArith64ExtOp.ValidOpcodes)>;

// Identify arithmetic immediate instructions.
def IsArithImmOp : CheckOpcode<[ADDWri, ADDXri, ADDSWri, ADDSXri,
SUBWri, SUBXri, SUBSWri, SUBSXri]>;
Expand Down Expand Up @@ -276,6 +282,28 @@ def IsCheapLSL : MCSchedPredicate<
CheckShiftBy3,
CheckShiftBy4]>]>>;

// Check for arith LSL shift <= 4
def IsCheapArithLSL : MCSchedPredicate<
CheckAll<
[CheckShiftLSL,
CheckAny<
[CheckExtBy0,
CheckExtBy1,
CheckExtBy2,
CheckExtBy3,
CheckExtBy4]>]>>;

// Check if logical instruction has shifted operand
def hasShiftedOpndFn : TIIPredicate<"hasShiftedOpnd",
MCOpcodeSwitchStatement<
[MCOpcodeSwitchCase<
IsLogicShiftOp.ValidOpcodes,
MCReturnStatement<
CheckAll<[CheckAny<[CheckShiftLSL,CheckShiftLSR,CheckShiftASR]>,
CheckNot<CheckShiftBy0>]>>>],
MCReturnStatement<FalsePred>>>;
def hasShiftedOpndPred : MCSchedPredicate<hasShiftedOpndFn>;

// Idioms.

// Identify an instruction that effectively transfers a register to another.
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/tools/llvm-mca/AArch64/Neoverse/512tvb-sve-instructions.s
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Expand Up @@ -14,7 +14,7 @@ abs z0.b, p0/m, z0.b
# CHECK-NEXT: [6]: HasSideEffects (U)

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 2 0.50 abs z0.b, p0/m, z0.b
# CHECK-NEXT: 2 2 0.50 abs z0.b, p0/m, z0.b

# CHECK: Resources:
# CHECK-NEXT: [0.0] - V1UnitB
Expand All @@ -38,8 +38,8 @@ abs z0.b, p0/m, z0.b

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11]
# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - -
# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [2.2] [3] [4.0] [4.1] [5] [6] [7.0] [7.1] [8] [9] [10] [11] Instructions:
# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - abs z0.b, p0/m, z0.b
# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 abs z0.b, p0/m, z0.b
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