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[TARGETS-PARSER] Added const reference for params with size >= 16 bytes #125083

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[TARGETS-PARSER] Added const reference for params with size >= 16 bytes #125083

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7 changes: 4 additions & 3 deletions llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
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Expand Up @@ -64,8 +64,8 @@ class AArch64ExpandPseudo : public MachineFunctionPass {
MachineBasicBlock::iterator &NextMBBI);
bool expandMultiVecPseudo(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
TargetRegisterClass ContiguousClass,
TargetRegisterClass StridedClass,
const TargetRegisterClass &ContiguousClass,
const TargetRegisterClass &StridedClass,
Comment on lines +67 to +68
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TargetRegisterClass certainly should never be passed by value. The actual pointer value is significant

unsigned ContiguousOpc, unsigned StridedOpc);
bool expandFormTuplePseudo(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
Expand Down Expand Up @@ -1121,7 +1121,8 @@ AArch64ExpandPseudo::expandCondSMToggle(MachineBasicBlock &MBB,

bool AArch64ExpandPseudo::expandMultiVecPseudo(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
TargetRegisterClass ContiguousClass, TargetRegisterClass StridedClass,
const TargetRegisterClass &ContiguousClass,
const TargetRegisterClass &StridedClass,
unsigned ContiguousOp, unsigned StridedOpc) {
MachineInstr &MI = *MBBI;
Register Tuple = MI.getOperand(0).getReg();
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
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Expand Up @@ -4252,7 +4252,7 @@ class TagStoreEdit {
}
// Add an instruction to be replaced. Instructions must be added in the
// ascending order of Offset, and have to be adjacent.
void addInstruction(TagStoreInstr I) {
void addInstruction(const TagStoreInstr &I) {
assert((TagStores.empty() ||
TagStores.back().Offset + TagStores.back().Size == I.Offset) &&
"Non-adjacent tag store instructions.");
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
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Expand Up @@ -38,8 +38,8 @@ SDValue AArch64SelectionDAGInfo::EmitMOPS(unsigned Opcode, SelectionDAG &DAG,
SDValue Dst, SDValue SrcOrValue,
SDValue Size, Align Alignment,
bool isVolatile,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const {
const MachinePointerInfo &DstPtrInfo,
const MachinePointerInfo &SrcPtrInfo) const {

// Get the constant size of the copy/set.
uint64_t ConstSize = 0;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
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Expand Up @@ -26,8 +26,8 @@ class AArch64SelectionDAGInfo : public SelectionDAGTargetInfo {
SDValue EmitMOPS(unsigned Opcode, SelectionDAG &DAG, const SDLoc &DL,
SDValue Chain, SDValue Dst, SDValue SrcOrValue, SDValue Size,
Align Alignment, bool isVolatile,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const;
const MachinePointerInfo &DstPtrInfo,
const MachinePointerInfo &SrcPtrInfo) const;

SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Dst, SDValue Src,
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
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Expand Up @@ -121,7 +121,7 @@ class TailFoldingOption {
return Bits;
}

void reportError(std::string Opt) {
void reportError(const std::string &Opt) {
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This should probably be Twine or StringRef

errs() << "invalid argument '" << Opt
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This doesn't look like an OK error handling strategy though

<< "' to -sve-tail-folding=; the option should be of the form\n"
" (disabled|all|default|simple)[+(reductions|recurrences"
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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Expand Up @@ -2455,7 +2455,7 @@ class AArch64Operand : public MCParsedAsmOperand {
}

static std::unique_ptr<AArch64Operand>
CreateFPImm(APFloat Val, bool IsExact, SMLoc S, MCContext &Ctx) {
CreateFPImm(const APFloat &Val, bool IsExact, SMLoc S, MCContext &Ctx) {
auto Op = std::make_unique<AArch64Operand>(k_FPImm, Ctx);
Op->FPImm.Val = Val.bitcastToAPInt().getSExtValue();
Op->FPImm.IsExact = IsExact;
Expand Down Expand Up @@ -3837,7 +3837,7 @@ static const struct Extension {
{"sme-tmop", {AArch64::FeatureSME_TMOP}},
};

static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
static void setRequiredFeatureString(const FeatureBitset &FBS, std::string &Str) {
if (FBS[AArch64::HasV8_0aOps])
Str += "ARMv8a";
if (FBS[AArch64::HasV8_1aOps])
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
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Expand Up @@ -373,7 +373,7 @@ struct SysAlias {
constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)
: Name(N), Encoding(E), FeaturesRequired(F) {}

bool haveFeatures(FeatureBitset ActiveFeatures) const {
bool haveFeatures(const FeatureBitset &ActiveFeatures) const {
return ActiveFeatures[llvm::AArch64::FeatureAll] ||
(FeaturesRequired & ActiveFeatures) == FeaturesRequired;
}
Expand Down Expand Up @@ -634,7 +634,7 @@ struct PHint {
unsigned Encoding;
FeatureBitset FeaturesRequired;

bool haveFeatures(FeatureBitset ActiveFeatures) const {
bool haveFeatures(const FeatureBitset &ActiveFeatures) const {
return ActiveFeatures[llvm::AArch64::FeatureAll] ||
(FeaturesRequired & ActiveFeatures) == FeaturesRequired;
}
Expand Down Expand Up @@ -753,7 +753,7 @@ namespace AArch64SysReg {
bool Writeable;
FeatureBitset FeaturesRequired;

bool haveFeatures(FeatureBitset ActiveFeatures) const {
bool haveFeatures(const FeatureBitset &ActiveFeatures) const {
return ActiveFeatures[llvm::AArch64::FeatureAll] ||
(FeaturesRequired & ActiveFeatures) == FeaturesRequired;
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUDelayedMCExpr.cpp
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Expand Up @@ -12,8 +12,8 @@

using namespace llvm;

static msgpack::DocNode getNode(msgpack::DocNode DN, msgpack::Type Type,
MCValue Val) {
static msgpack::DocNode getNode(const msgpack::DocNode &DN, msgpack::Type Type,
const MCValue &Val) {
msgpack::Document *Doc = DN.getDocument();
switch (Type) {
default:
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/ARM/ARMInstructionSelector.cpp
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Expand Up @@ -44,13 +44,13 @@ class ARMInstructionSelector : public InstructionSelector {
struct CmpConstants;
struct InsertInfo;

bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
bool selectCmp(const CmpConstants &Helper, MachineInstrBuilder &MIB,
MachineRegisterInfo &MRI) const;

// Helper for inserting a comparison sequence that sets \p ResReg to either 1
// if \p LHSReg and \p RHSReg are in the relationship defined by \p Cond, or
// \p PrevRes otherwise. In essence, it computes PrevRes OR (LHS Cond RHS).
bool insertComparison(CmpConstants Helper, InsertInfo I, unsigned ResReg,
bool insertComparison(const CmpConstants &Helper, InsertInfo I, unsigned ResReg,
ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
unsigned PrevRes) const;

Expand Down Expand Up @@ -525,7 +525,7 @@ bool ARMInstructionSelector::validReg(MachineRegisterInfo &MRI, unsigned Reg,
return true;
}

bool ARMInstructionSelector::selectCmp(CmpConstants Helper,
bool ARMInstructionSelector::selectCmp(const CmpConstants &Helper,
MachineInstrBuilder &MIB,
MachineRegisterInfo &MRI) const {
const InsertInfo I(MIB);
Expand Down Expand Up @@ -572,7 +572,7 @@ bool ARMInstructionSelector::selectCmp(CmpConstants Helper,
return true;
}

bool ARMInstructionSelector::insertComparison(CmpConstants Helper, InsertInfo I,
bool ARMInstructionSelector::insertComparison(const CmpConstants &Helper, InsertInfo I,
unsigned ResReg,
ARMCC::CondCodes Cond,
unsigned LHSReg, unsigned RHSReg,
Expand Down
10 changes: 6 additions & 4 deletions llvm/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
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Expand Up @@ -27,13 +27,15 @@ class ARMMachObjectWriter : public MCMachObjectTargetWriter {
void recordARMScatteredRelocation(MachObjectWriter *Writer,
const MCAssembler &Asm,
const MCFragment *Fragment,
const MCFixup &Fixup, MCValue Target,
const MCFixup &Fixup,
const MCValue &Target,
unsigned Type, unsigned Log2Size,
uint64_t &FixedValue);
void recordARMScatteredHalfRelocation(MachObjectWriter *Writer,
const MCAssembler &Asm,
const MCFragment *Fragment,
const MCFixup &Fixup, MCValue Target,
const MCFixup &Fixup,
const MCValue &Target,
uint64_t &FixedValue);

bool requiresExternRelocation(MachObjectWriter *Writer,
Expand Down Expand Up @@ -130,7 +132,7 @@ static bool getARMFixupKindMachOInfo(unsigned Kind, unsigned &RelocType,

void ARMMachObjectWriter::recordARMScatteredHalfRelocation(
MachObjectWriter *Writer, const MCAssembler &Asm,
const MCFragment *Fragment, const MCFixup &Fixup, MCValue Target,
const MCFragment *Fragment, const MCFixup &Fixup, const MCValue &Target,
uint64_t &FixedValue) {
uint32_t FixupOffset = Asm.getFragmentOffset(*Fragment) + Fixup.getOffset();

Expand Down Expand Up @@ -240,7 +242,7 @@ void ARMMachObjectWriter::recordARMScatteredHalfRelocation(

void ARMMachObjectWriter::recordARMScatteredRelocation(
MachObjectWriter *Writer, const MCAssembler &Asm,
const MCFragment *Fragment, const MCFixup &Fixup, MCValue Target,
const MCFragment *Fragment, const MCFixup &Fixup, const MCValue &Target,
unsigned Type, unsigned Log2Size, uint64_t &FixedValue) {
uint32_t FixupOffset = Asm.getFragmentOffset(*Fragment) + Fixup.getOffset();

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
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Expand Up @@ -196,12 +196,12 @@ namespace ARMSysReg {
FeatureBitset FeaturesRequired;

// return true if FeaturesRequired are all present in ActiveFeatures
bool hasRequiredFeatures(FeatureBitset ActiveFeatures) const {
bool hasRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
}

// returns true if TestFeatures are all present in FeaturesRequired
bool isInRequiredFeatures(FeatureBitset TestFeatures) const {
bool isInRequiredFeatures(const FeatureBitset &TestFeatures) const {
return (FeaturesRequired & TestFeatures) == TestFeatures;
}
};
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp
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Expand Up @@ -32,7 +32,7 @@ namespace adjust {
using namespace llvm;

static void unsigned_width(unsigned Width, uint64_t Value,
std::string Description, const MCFixup &Fixup,
const std::string &Description, const MCFixup &Fixup,
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This should be using StringRef, and the code below should be using Twine instead of building the string itself

MCContext *Ctx) {
if (!isUIntN(Width, Value)) {
std::string Diagnostic = "out of range " + Description;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
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Expand Up @@ -202,7 +202,7 @@ namespace {
Pos = std::distance(B->begin(), It);
}
}
bool operator<(Loc A) const {
bool operator<(const Loc &A) const {
if (Block != A.Block)
return Block->getNumber() < A.Block->getNumber();
if (A.Pos == -1)
Expand Down
40 changes: 20 additions & 20 deletions llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
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Expand Up @@ -949,7 +949,7 @@ namespace llvm {
void selectRor(SDNode *N);
void selectVAlign(SDNode *N);

static SmallVector<uint32_t, 8> getPerfectCompletions(ShuffleMask SM,
static SmallVector<uint32_t, 8> getPerfectCompletions(const ShuffleMask &SM,
unsigned Width);
static SmallVector<uint32_t, 8> completeToPerfect(
ArrayRef<uint32_t> Completions, unsigned Width);
Expand All @@ -966,22 +966,22 @@ namespace llvm {
None,
PackMux,
};
OpRef concats(OpRef Va, OpRef Vb, ResultStack &Results);
OpRef concats(const OpRef &Va, const OpRef &Vb, ResultStack &Results);
OpRef funnels(OpRef Va, OpRef Vb, int Amount, ResultStack &Results);

OpRef packs(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results,
MutableArrayRef<int> NewMask, unsigned Options = None);
OpRef packp(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results,
OpRef packp(const ShuffleMask &SM, const OpRef &Va, const OpRef &Vb, ResultStack &Results,
MutableArrayRef<int> NewMask);
OpRef vmuxs(ArrayRef<uint8_t> Bytes, OpRef Va, OpRef Vb,
OpRef vmuxs(ArrayRef<uint8_t> Bytes, const OpRef &Va, const OpRef &Vb,
ResultStack &Results);
OpRef vmuxp(ArrayRef<uint8_t> Bytes, OpRef Va, OpRef Vb,
OpRef vmuxp(ArrayRef<uint8_t> Bytes, const OpRef &Va, const OpRef &Vb,
ResultStack &Results);

OpRef shuffs1(ShuffleMask SM, OpRef Va, ResultStack &Results);
OpRef shuffs2(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results);
OpRef shuffp1(ShuffleMask SM, OpRef Va, ResultStack &Results);
OpRef shuffp2(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results);
OpRef shuffs1(ShuffleMask SM, const OpRef &Va, ResultStack &Results);
OpRef shuffs2(const ShuffleMask &SM, const OpRef &Va, const OpRef &Vb, ResultStack &Results);
OpRef shuffp1(const ShuffleMask &SM, const OpRef &Va, ResultStack &Results);
OpRef shuffp2(const ShuffleMask &SM, const OpRef &Va, const OpRef &Vb, ResultStack &Results);

OpRef butterfly(ShuffleMask SM, OpRef Va, ResultStack &Results);
OpRef contracting(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results);
Expand Down Expand Up @@ -1048,7 +1048,7 @@ static bool isLowHalfOnly(ArrayRef<int> Mask) {
return llvm::all_of(Mask.drop_front(L / 2), [](int M) { return M < 0; });
}

static SmallVector<unsigned, 4> getInputSegmentList(ShuffleMask SM,
static SmallVector<unsigned, 4> getInputSegmentList(const ShuffleMask &SM,
unsigned SegLen) {
assert(isPowerOf2_32(SegLen));
SmallVector<unsigned, 4> SegList;
Expand All @@ -1068,7 +1068,7 @@ static SmallVector<unsigned, 4> getInputSegmentList(ShuffleMask SM,
return SegList;
}

static SmallVector<unsigned, 4> getOutputSegmentMap(ShuffleMask SM,
static SmallVector<unsigned, 4> getOutputSegmentMap(const ShuffleMask &SM,
unsigned SegLen) {
// Calculate the layout of the output segments in terms of the input
// segments.
Expand Down Expand Up @@ -1213,7 +1213,7 @@ void HvxSelector::materialize(const ResultStack &Results) {
DAG.RemoveDeadNodes();
}

OpRef HvxSelector::concats(OpRef Lo, OpRef Hi, ResultStack &Results) {
OpRef HvxSelector::concats(const OpRef &Lo, const OpRef &Hi, ResultStack &Results) {
DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
const SDLoc &dl(Results.InpNode);
Results.push(TargetOpcode::REG_SEQUENCE, getPairVT(MVT::i8), {
Expand Down Expand Up @@ -1496,7 +1496,7 @@ OpRef HvxSelector::packs(ShuffleMask SM, OpRef Va, OpRef Vb,
// Va, Vb are vector pairs. If SM only uses two single vectors from Va/Vb,
// pack these vectors into a pair, and remap SM into NewMask to use the
// new pair instead.
OpRef HvxSelector::packp(ShuffleMask SM, OpRef Va, OpRef Vb,
OpRef HvxSelector::packp(const ShuffleMask &SM, const OpRef &Va, const OpRef &Vb,
ResultStack &Results, MutableArrayRef<int> NewMask) {
DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
SmallVector<unsigned, 4> SegList = getInputSegmentList(SM.Mask, HwLen);
Expand Down Expand Up @@ -1533,7 +1533,7 @@ OpRef HvxSelector::packp(ShuffleMask SM, OpRef Va, OpRef Vb,
return concats(Out[0], Out[1], Results);
}

OpRef HvxSelector::vmuxs(ArrayRef<uint8_t> Bytes, OpRef Va, OpRef Vb,
OpRef HvxSelector::vmuxs(ArrayRef<uint8_t> Bytes, const OpRef &Va, const OpRef &Vb,
ResultStack &Results) {
DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
MVT ByteTy = getSingleVT(MVT::i8);
Expand All @@ -1546,7 +1546,7 @@ OpRef HvxSelector::vmuxs(ArrayRef<uint8_t> Bytes, OpRef Va, OpRef Vb,
return OpRef::res(Results.top());
}

OpRef HvxSelector::vmuxp(ArrayRef<uint8_t> Bytes, OpRef Va, OpRef Vb,
OpRef HvxSelector::vmuxp(ArrayRef<uint8_t> Bytes, const OpRef &Va, const OpRef &Vb,
ResultStack &Results) {
DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
size_t S = Bytes.size() / 2;
Expand All @@ -1555,7 +1555,7 @@ OpRef HvxSelector::vmuxp(ArrayRef<uint8_t> Bytes, OpRef Va, OpRef Vb,
return concats(L, H, Results);
}

OpRef HvxSelector::shuffs1(ShuffleMask SM, OpRef Va, ResultStack &Results) {
OpRef HvxSelector::shuffs1(ShuffleMask SM, const OpRef &Va, ResultStack &Results) {
DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
unsigned VecLen = SM.Mask.size();
assert(HwLen == VecLen);
Expand Down Expand Up @@ -1598,7 +1598,7 @@ OpRef HvxSelector::shuffs1(ShuffleMask SM, OpRef Va, ResultStack &Results) {
return butterfly(SM, Va, Results);
}

OpRef HvxSelector::shuffs2(ShuffleMask SM, OpRef Va, OpRef Vb,
OpRef HvxSelector::shuffs2(const ShuffleMask &SM, const OpRef &Va, const OpRef &Vb,
ResultStack &Results) {
DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
if (isUndef(SM.Mask))
Expand Down Expand Up @@ -1633,7 +1633,7 @@ OpRef HvxSelector::shuffs2(ShuffleMask SM, OpRef Va, OpRef Vb,
return vmuxs(Bytes, L, R, Results);
}

OpRef HvxSelector::shuffp1(ShuffleMask SM, OpRef Va, ResultStack &Results) {
OpRef HvxSelector::shuffp1(const ShuffleMask &SM, const OpRef &Va, ResultStack &Results) {
DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
int VecLen = SM.Mask.size();

Expand Down Expand Up @@ -1676,7 +1676,7 @@ OpRef HvxSelector::shuffp1(ShuffleMask SM, OpRef Va, ResultStack &Results) {
return OpRef::fail();
}

OpRef HvxSelector::shuffp2(ShuffleMask SM, OpRef Va, OpRef Vb,
OpRef HvxSelector::shuffp2(const ShuffleMask &SM, const OpRef &Va, const OpRef &Vb,
ResultStack &Results) {
DEBUG_WITH_TYPE("isel", {dbgs() << __func__ << '\n';});
if (isUndef(SM.Mask))
Expand Down Expand Up @@ -1917,7 +1917,7 @@ bool HvxSelector::scalarizeShuffle(ArrayRef<int> Mask, const SDLoc &dl,
return true;
}

SmallVector<uint32_t, 8> HvxSelector::getPerfectCompletions(ShuffleMask SM,
SmallVector<uint32_t, 8> HvxSelector::getPerfectCompletions(const ShuffleMask &SM,
unsigned Width) {
auto possibilities = [](ArrayRef<uint8_t> Bs, unsigned Width) -> uint32_t {
unsigned Impossible = ~(1u << Width) + 1;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
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Expand Up @@ -1822,7 +1822,7 @@ void NVPTXAsmPrinter::printFPConstant(const ConstantFP *Fp, raw_ostream &O) {
} else
llvm_unreachable("unsupported fp type");

APInt API = APF.bitcastToAPInt();
const APInt &API = APF.bitcastToAPInt();
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bitcastToAPInt returns a new APInt not a reference. So this creates a reference to a temporary object which works but seems like an uneccessary change.

O << lead << format_hex_no_prefix(API.getZExtValue(), numHex, /*Upper=*/true);
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/NVPTX/NVPTXMCExpr.cpp
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Expand Up @@ -51,7 +51,7 @@ void NVPTXFloatMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
break;
}

APInt API = APF.bitcastToAPInt();
const APInt &API = APF.bitcastToAPInt();
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bitcastToAPInt returns a new APInt not a reference.

OS << format_hex_no_prefix(API.getZExtValue(), NumHex, /*Upper=*/true);
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/TargetParser/ARMTargetParser.cpp
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Expand Up @@ -650,7 +650,7 @@ StringRef ARM::getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch) {
llvm_unreachable("invalid arch name");
}

void ARM::PrintSupportedExtensions(StringMap<StringRef> DescMap) {
void ARM::PrintSupportedExtensions(StringMap<StringRef> &DescMap) {
outs() << "All available -march extensions for ARM\n\n"
<< " " << left_justify("Name", 20)
<< (DescMap.empty() ? "\n" : "Description\n");
Expand Down