[Xtensa] Implement Windowed Register Option. #124656
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@llvm/pr-subscribers-backend-xtensa @llvm/pr-subscribers-mc Author: Andrei Safronov (andreisfr) ChangesThis second version of the Windowed Register Option implementation. In this variant "checkRegister" function placed in XtensaMCTargetDesc. Patch is 30.90 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/124656.diff 18 Files Affected:
diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
index 731f9535ca251f..0c9258ecd65ecb 100644
--- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
+++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
@@ -73,6 +73,7 @@ class XtensaAsmParser : public MCTargetAsmParser {
SMLoc &EndLoc) override {
return ParseStatus::NoMatch;
}
+
ParseStatus parsePCRelTarget(OperandVector &Operands);
bool parseLiteralDirective(SMLoc L);
@@ -89,6 +90,10 @@ class XtensaAsmParser : public MCTargetAsmParser {
: MCTargetAsmParser(Options, STI, MII) {
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
}
+
+ bool hasWindowed() const {
+ return getSTI().getFeatureBits()[Xtensa::FeatureWindowed];
+ };
};
// Return true if Expr is in the range [MinValue, MaxValue].
@@ -181,6 +186,11 @@ struct XtensaOperand : public MCParsedAsmOperand {
((cast<MCConstantExpr>(getImm())->getValue() & 0x3) == 0);
}
+ bool isentry_imm12() const {
+ return isImm(0, 32760) &&
+ ((cast<MCConstantExpr>(getImm())->getValue() % 8) == 0);
+ }
+
bool isUimm4() const { return isImm(0, 15); }
bool isUimm5() const { return isImm(0, 31); }
@@ -198,6 +208,11 @@ struct XtensaOperand : public MCParsedAsmOperand {
bool isImm32n_95() const { return isImm(-32, 95); }
+ bool isImm64n_4n() const {
+ return isImm(-64, -4) &&
+ ((cast<MCConstantExpr>(getImm())->getValue() & 0x3) == 0);
+ }
+
bool isB4const() const {
if (Kind != Immediate)
return false;
@@ -491,6 +506,12 @@ bool XtensaAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidImm32n_95:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected immediate in range [-32, 95]");
+ case Match_InvalidImm64n_4n:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [-64, -4]");
+ case Match_InvalidImm8n_7:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [-8, 7]");
case Match_InvalidShimm1_31:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected immediate in range [1, 31]");
@@ -515,6 +536,10 @@ bool XtensaAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected immediate in range [0, 60], first 2 bits "
"should be zero");
+ case Match_Invalidentry_imm12:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [0, 32760], first 3 bits "
+ "should be zero");
}
report_fatal_error("Unknown match type detected!");
@@ -601,6 +626,10 @@ ParseStatus XtensaAsmParser::parseRegister(OperandVector &Operands,
getLexer().UnLex(Buf[0]);
return ParseStatus::NoMatch;
}
+
+ if (!Xtensa::checkRegister(RegNo, getSTI().getFeatureBits()))
+ return ParseStatus::NoMatch;
+
if (HadParens)
Operands.push_back(XtensaOperand::createToken("(", FirstS));
SMLoc S = getLoc();
@@ -702,7 +731,7 @@ bool XtensaAsmParser::ParseInstructionWithSR(ParseInstructionInfo &Info,
if (RegNo == 0)
RegNo = MatchRegisterAltName(RegName);
- if (RegNo == 0)
+ if (!Xtensa::checkRegister(RegNo, getSTI().getFeatureBits()))
return Error(NameLoc, "invalid register name");
// Parse operand
diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
index c11c4b7038bdb7..9f9e832fd8c7e4 100644
--- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
+++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
@@ -9,7 +9,19 @@
//===----------------------------------------------------------------------===//
//
// This file implements the XtensaDisassembler class.
-//
+//#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCDecoderOps.h"
+#include "llvm/MC/MCDisassembler/MCDisassembler.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "Xtensa-disassembler"
+
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/XtensaMCTargetDesc.h"
@@ -73,17 +85,23 @@ static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo,
return MCDisassembler::Success;
}
-static const unsigned SRDecoderTable[] = {Xtensa::SAR, 3};
+static const unsigned SRDecoderTable[] = {
+ Xtensa::SAR, 3, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73};
static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
if (RegNo > 255)
return MCDisassembler::Fail;
for (unsigned i = 0; i < std::size(SRDecoderTable); i += 2) {
if (SRDecoderTable[i + 1] == RegNo) {
unsigned Reg = SRDecoderTable[i];
+
+ if (!Xtensa::checkRegister(Reg,
+ Decoder->getSubtargetInfo().getFeatureBits()))
+ return MCDisassembler::Fail;
+
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -210,6 +228,29 @@ static DecodeStatus decodeImm32n_95Operand(MCInst &Inst, uint64_t Imm,
return MCDisassembler::Success;
}
+static DecodeStatus decodeImm8n_7Operand(MCInst &Inst, uint64_t Imm,
+ int64_t Address, const void *Decoder) {
+ assert(isUInt<4>(Imm) && "Invalid immediate");
+ Inst.addOperand(MCOperand::createImm(Imm > 7 ? Imm - 16 : Imm));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeImm64n_4nOperand(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isUInt<6>(Imm) && ((Imm & 0x3) == 0) && "Invalid immediate");
+ Inst.addOperand(MCOperand::createImm((~0x3f) | (Imm)));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeEntry_Imm12OpValue(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isUInt<15>(Imm) && ((Imm & 0x7) == 0) && "Invalid immediate");
+ Inst.addOperand(MCOperand::createImm(Imm));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus decodeShimm1_31Operand(MCInst &Inst, uint64_t Imm,
int64_t Address,
const void *Decoder) {
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
index df8a0854f06f41..868c7f6c0b9c3c 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
@@ -264,6 +264,28 @@ void XtensaInstPrinter::printImm32n_95_AsmOperand(const MCInst *MI, int OpNum,
printOperand(MI, OpNum, O);
}
+void XtensaInstPrinter::printImm8n_7_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ if (MI->getOperand(OpNum).isImm()) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ assert((Value >= -8 && Value <= 7) &&
+ "Invalid argument, value must be in ranges <-8,7>");
+ O << Value;
+ } else
+ printOperand(MI, OpNum, O);
+}
+
+void XtensaInstPrinter::printImm64n_4n_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ if (MI->getOperand(OpNum).isImm()) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ assert((Value >= -64 && Value <= -4) & ((Value & 0x3) == 0) &&
+ "Invalid argument, value must be in ranges <-64,-4>");
+ O << Value;
+ } else
+ printOperand(MI, OpNum, O);
+}
+
void XtensaInstPrinter::printOffset8m8_AsmOperand(const MCInst *MI, int OpNum,
raw_ostream &O) {
if (MI->getOperand(OpNum).isImm()) {
@@ -309,6 +331,18 @@ void XtensaInstPrinter::printOffset4m32_AsmOperand(const MCInst *MI, int OpNum,
printOperand(MI, OpNum, O);
}
+void XtensaInstPrinter::printEntry_Imm12_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ if (MI->getOperand(OpNum).isImm()) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ assert((Value >= 0 && Value <= 32760) &&
+ "Invalid argument, value must be multiples of eight in range "
+ "<0,32760>");
+ O << Value;
+ } else
+ printOperand(MI, OpNum, O);
+}
+
void XtensaInstPrinter::printB4const_AsmOperand(const MCInst *MI, int OpNum,
raw_ostream &O) {
if (MI->getOperand(OpNum).isImm()) {
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
index e5bc67869e103d..630b4dd60108ff 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
@@ -60,10 +60,13 @@ class XtensaInstPrinter : public MCInstPrinter {
void printImm1_16_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printImm1n_15_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printImm32n_95_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printImm8n_7_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printImm64n_4n_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printOffset8m8_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printOffset8m16_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printOffset8m32_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printOffset4m32_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printEntry_Imm12_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printB4const_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printB4constu_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
};
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
index 51d4b8a9cc5fc5..e6cdd3d0020fc0 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
@@ -111,6 +111,18 @@ class XtensaMCCodeEmitter : public MCCodeEmitter {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+ uint32_t getImm8n_7OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
+ uint32_t getImm64n_4nOpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
+ uint32_t getEntry_Imm12OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
uint32_t getShimm1_31OpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
@@ -405,6 +417,46 @@ XtensaMCCodeEmitter::getImm32n_95OpValue(const MCInst &MI, unsigned OpNo,
return Res;
}
+uint32_t
+XtensaMCCodeEmitter::getImm8n_7OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+ int32_t Res = static_cast<int32_t>(MO.getImm());
+
+ assert(((Res >= -8) && (Res <= 7)) && "Unexpected operand value!");
+
+ if (Res < 0)
+ return Res + 16;
+
+ return Res;
+}
+
+uint32_t
+XtensaMCCodeEmitter::getImm64n_4nOpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+ int32_t Res = static_cast<int32_t>(MO.getImm());
+
+ assert(((Res >= -64) && (Res <= -4) && ((Res & 0x3) == 0)) &&
+ "Unexpected operand value!");
+
+ return Res & 0x3f;
+}
+
+uint32_t
+XtensaMCCodeEmitter::getEntry_Imm12OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+ uint32_t res = static_cast<uint32_t>(MO.getImm());
+
+ assert(((res & 0x7) == 0) && "Unexpected operand value!");
+
+ return res;
+}
+
uint32_t
XtensaMCCodeEmitter::getB4constOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
index fc23c2356825f3..37dee072e5b3dd 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
@@ -74,6 +74,19 @@ bool Xtensa::isValidAddrOffsetForOpcode(unsigned Opcode, int64_t Offset) {
return isValidAddrOffset(Scale, Offset);
}
+// Verify Special Register
+bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits) {
+ switch (RegNo) {
+ case Xtensa::WINDOWBASE:
+ case Xtensa::WINDOWSTART:
+ return FeatureBits[Xtensa::FeatureWindowed];
+ case Xtensa::NoRegister:
+ return false;
+ }
+
+ return true;
+}
+
static MCAsmInfo *createXtensaMCAsmInfo(const MCRegisterInfo &MRI,
const Triple &TT,
const MCTargetOptions &Options) {
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
index 6be54867d84a73..649073b01f5c10 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
@@ -19,12 +19,14 @@
namespace llvm {
+class FeatureBitset;
class MCAsmBackend;
class MCCodeEmitter;
class MCContext;
class MCInstrInfo;
class MCObjectTargetWriter;
class MCObjectWriter;
+class MCRegister;
class MCRegisterInfo;
class MCSubtargetInfo;
class MCTargetOptions;
@@ -52,6 +54,9 @@ bool isValidAddrOffset(int Scale, int64_t OffsetVal);
// Check address offset for load/store instructions.
bool isValidAddrOffsetForOpcode(unsigned Opcode, int64_t Offset);
+
+// Verify if it's correct to use a special register.
+bool checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits);
} // namespace Xtensa
} // end namespace llvm
diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td
index 460a15e808b3a4..2c4bacbe8282b0 100644
--- a/llvm/lib/Target/Xtensa/Xtensa.td
+++ b/llvm/lib/Target/Xtensa/Xtensa.td
@@ -17,10 +17,9 @@ include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// Subtarget Features.
//===----------------------------------------------------------------------===//
-def FeatureDensity : SubtargetFeature<"density", "HasDensity", "true",
- "Enable Density instructions">;
-def HasDensity : Predicate<"Subtarget->hasDensity()">,
- AssemblerPredicate<(all_of FeatureDensity)>;
+
+include "XtensaFeatures.td"
+
//===----------------------------------------------------------------------===//
// Xtensa supported processors.
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaFeatures.td b/llvm/lib/Target/Xtensa/XtensaFeatures.td
new file mode 100644
index 00000000000000..6f24a674ae0ce2
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaFeatures.td
@@ -0,0 +1,14 @@
+//===----------------------------------------------------------------------===//
+// Xtensa subtarget features.
+//===----------------------------------------------------------------------===//
+
+// Xtensa ISA extensions (Xtensa Options).
+def FeatureDensity : SubtargetFeature<"density", "HasDensity", "true",
+ "Enable Density instructions">;
+def HasDensity : Predicate<"Subtarget->hasDensity()">,
+ AssemblerPredicate<(all_of FeatureDensity)>;
+
+def FeatureWindowed : SubtargetFeature<"windowed", "HasWindowed", "true",
+ "Enable Xtensa Windowed Register option">;
+def HasWindowed : Predicate<"Subtarget->hasWindowed()">,
+ AssemblerPredicate<(all_of FeatureWindowed)>;
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
index 699d0d6cf80445..5ef795a0e5287a 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -678,3 +678,104 @@ let isReturn = 1, isTerminator = 1,
let t = 0;
}
}
+
+//===----------------------------------------------------------------------===//
+// Windowed instructions
+//===----------------------------------------------------------------------===//
+
+def ENTRY : BRI12_Inst<0x06, 0x3, 0x0, (outs), (ins AR:$s, entry_imm12:$imm),
+ "entry\t$s, $imm", []>, Requires<[HasWindowed]> {
+ bits<15> imm;
+
+ let imm12{11-0} = imm{14-3};
+ let Defs = [SP];
+}
+
+let isCall = 1, Defs = [A0] in {
+ foreach i = {1,2,3} in {
+ defvar I = !mul(4, i);
+
+ def CALL#I# : CALL_Inst<0x05, (outs), (ins pcrel32call:$offset),
+ "call"#I#"\t$offset", []>, Requires<[HasWindowed]> {
+ let n = i;
+ }
+
+ def CALLX#I# : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins AR:$s),
+ "callx"#I#"\t$s", []>, Requires<[HasWindowed]> {
+ let m = 0x3;
+ let n = i;
+ let r = 0;
+ }
+ }
+}
+
+def MOVSP : RRR_Inst<0x00, 0x00, 0x00, (outs AR:$t), (ins AR:$s),
+ "movsp\t$t, $s", []>, Requires<[HasWindowed]> {
+ let r = 0x01;
+}
+
+let isReturn = 1, isTerminator = 1,
+ isBarrier = 1, Uses = [A0] in {
+ def RETW_N : RRRN_Inst<0x0D, (outs), (ins),
+ "retw.n", []>, Requires<[HasWindowed, HasDensity]> {
+ let r = 0x0F;
+ let s = 0;
+ let t = 1;
+ }
+
+ def RETW : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins),
+ "retw", []>, Requires<[HasWindowed]> {
+ let m = 0x2;
+ let n = 0x1;
+ let s = 0;
+ let r = 0;
+ }
+}
+
+def : InstAlias<"_retw", (RETW)>;
+def : InstAlias<"_retw.n", (RETW_N)>;
+
+def S32E : RRI4_Inst<0x00, 0x09, (outs), (ins AR:$t, AR:$s, imm64n_4n:$imm),
+ "s32e\t$t, $s, $imm", []>, Requires<[HasWindowed]> {
+ bits<6> imm;
+
+ let r = imm{5-2};
+ let imm4 = 0x4;
+ let mayStore = 1;
+}
+
+def L32E : RRI4_Inst<0x00, 0x09, (outs), (ins AR:$t, AR:$s, imm64n_4n:$imm),
+ "l32e\t$t, $s, $imm", []>, Requires<[HasWindowed]> {
+ bits<6> imm;
+
+ let r = imm{5-2};
+ let imm4 = 0x0;
+ let mayLoad = 1;
+}
+
+def RFWU : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),
+ "rfwu", []>, Requires<[HasWindowed]> {
+ bits<4> imm;
+
+ let r = 0x3;
+ let s = 0x5;
+ let t = 0x0;
+}
+
+def RFWO : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),
+ "rfwo", []>, Requires<[HasWindowed]> {
+ bits<4> imm;
+
+ let r = 0x3;
+ let s = 0x4;
+ let t = 0x0;
+}
+
+def ROTW : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins imm8n_7:$imm),
+ "rotw\t$imm", []>, Requires<[HasWindowed]> {
+ bits<4> imm;
+
+ let r = 0x8;
+ let s = 0x0;
+ let t = imm{3-0};
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaOperands.td b/llvm/lib/Target/Xtensa/XtensaOperands.td
index aa72...
[truncated]
|
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
|
Previous PR which implemented "WIndowed register option" #121118 was reviewed and merged, but then reverted because there was a link error to checkRegister function from AsmParser and Disassembler modules. In this variant "checkRegister" function placed in XtensaMCTargetDesc. |
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arsenm
approved these changes
Jan 28, 2025
|
For reland, best to include the full description of the initial one. Also mention the original PR in the description (commit message). Oh, the initial PR has an empty description #121118 ... |
MaskRay
reviewed
Jan 29, 2025
| @@ -0,0 +1,105 @@ | |||
| # RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+windowed \ | |||
There was a problem hiding this comment.
You might want to adopt llvm/utils/update_mc_test_checks.py
There was a problem hiding this comment.
@MaskRay, thank you very much for comments. I used update_mc_test_checks.py to update tests. All tests updated except "llvm/test/MC/Xtensa/windowed.s". It seems script produces incorrect result.
For asm code:
call4 LBL0 # encoding: [0bAA010101,A,A]
# fixup A - offset: 0, value: LBL0, kind: fixup_xtensa_call_18
this utility generates:
// CHECK: call4 LBL0 # encoding: [0bAA010101,A,A]# fixup A - offset: 0, value: LBL0, kind: fixup_xtensa_call_18
instead of for example:
// CHECK: call4 LBL0 # encoding: [0bAA010101,A,A]
// CHECK-NEXT: # fixup A - offset: 0, value: LBL0, kind: fixup_xtensa_call_18
So, maybe we should investigate and prepare fix for this problem?
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Yes, you might want to port the tool to Xtensa and then add a test to llvm/test/tools/UpdateTestChecks/update_mc_test_checks/
MaskRay
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Jan 29, 2025
MaskRay
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Jan 30, 2025
| @@ -73,17 +73,23 @@ static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo, | |||
| return MCDisassembler::Success; | |||
| } | |||
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| static const unsigned SRDecoderTable[] = {Xtensa::SAR, 3}; | |||
| static const unsigned SRDecoderTable[] = { | |||
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can omit static since const at a namespace scope by default has the internal linkage
This patch implements Xtensa ISA option "Windowed Register Option". It implements subtarget feature, instructions descriptions and support of these instruction in asm parser and disassembler. This is the second version of the Windowed Register Option implementation. Previous implementation llvm#121118. In this variant "checkRegister" function placed in XtensaMCTargetDesc.
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I added more information to the first commit message. |
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There is an undefined reference to checkRegister in shared builds Suspecting llvm#124656
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There is an undefined reference to checkRegister in shared lib builds Suspecting #124656
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…6904) There is an undefined reference to checkRegister in shared lib builds Suspecting llvm#124656
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…6904) There is an undefined reference to checkRegister in shared lib builds Suspecting llvm#124656
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…6904) There is an undefined reference to checkRegister in shared lib builds Suspecting llvm#124656
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This second version of the Windowed Register Option implementation. In this variant "checkRegister" function placed in XtensaMCTargetDesc.